Datasheet

M48T02, M48T12 Operation modes
Doc ID 2410 Rev 9 7/25
2 Operation modes
As Figure 3 on page 6 shows, the static memory array and the quartz controlled clock
oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations
contain the year, month, date, day, hour, minute, and second in 24-hour BCD format.
Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made
automatically.
Byte 7F8h is the clock control register. This byte controls user access to the clock
information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
CC
is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below
approximately 3 V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
Table 2. Operating modes
Note: X = V
IH
or V
IL
; V
SO
= Battery backup switchover voltage.
2.1 READ mode
The M48T02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If
the E
and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
ELQV
) or output enable access time (t
GLQV
).
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
V
IH
X X High Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High Z Active
Deselect
V
SO
to
V
PFD
(min)
(1)
1. See Table 11 on page 20 for details.
X X X High Z CMOS standby
Deselect ≤ V
SO
(1)
X X X High Z Battery backup mode