Datasheet

Operation M41T94
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3 Operation
The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL,
SDI and SDO (see Table 1 on page 8 and Figure 5 on page 9). The device is selected when
the chip enable input (E
) is held low. All instructions, addresses and data are shifted serially
in and out of the chip. The most significant bit is presented first, with the data input (SDI)
sampled on the first rising edge of the clock (SCL) after the chip enable (E
) goes low. The 64
bytes contained in the device can then be accessed sequentially in the following order:
● 1
st
byte: tenths/hundredths of a second register
● 2
nd
byte: seconds register
● 3
rd
byte: minutes register
● 4
th
byte: century/hours register
● 5
th
byte: day register
● 6
th
byte: date register
● 7
th
byte: month register
● 8
th
byte: year register
● 9
th
byte: control register
● 10
th
byte: watchdog register
● 11
th
- 16
th
bytes: Alarm registers
● 17
th
- 19
th
bytes: reserved
● 20
th
byte: square wave register
● 21
st
- 64
th
bytes: user RAM
The M41T94 clock continually monitors V
CC
for an out-of tolerance condition. Should V
CC
fall below V
PFD
, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. When V
CC
falls below
V
SO
, the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. As system power returns and V
CC
rises
above V
SO
, the battery is disconnected, and the power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches V
PFD
(min) plus t
REC
(min). For more
information on battery storage life refer to application note AN1012.