Datasheet

Operation M41T94
14/41
Figure 8. Output timing requirements
AI04634
SCL
SDO
E
LSB OUT
SDI
ADDR. LSB IN
tEHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
MSB OUT
Table 3. AC characteristics
Symbol Parameter
(1)
Min Max Unit
f
SCL
Serial clock input frequency DC 2 MHz
t
CH
(2)
Clock high 200 ns
t
CHCL
(3)
Clock transition (fall time) 1 µs
t
CHDX
Serial clock input high to input data transition 50 ns
t
CHEH
Serial clock input high to chip enable high 200 ns
t
CL
(2)
Clock low 200 ns
t
CLCH
(3)
Clock transition (rise time) 1 µs
t
CLQV
Serial clock input low to output valid 150 ns
t
CLQX
Serial clock input low to output data transition 0 ns
t
DHDL
(3)
Input data transition (fall time) 1 µs
t
DLDH
(3)
Input data transition (rise time) 1 µs
t
DVCH
Input data to serial clock input high 40 ns
t
EHCH
Chip enable high to serial clock input high 200 ns
t
EHEL
Chip enable high to chip enable low 200 ns
t
EHQZ
(3)
Chip enable high to output high-z 250 ns
t
ELCH
Chip enable low to serial clock input high 200 ns
t
QHQL
(3)
Output data transition (fall time) 100 ns
t
QLQH
(3)
Output data transition (rise time) 100 ns
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5 V (except where noted).
2. t
CH
+ t
CL
≥ 1/f
SCL
3. Value guaranteed by design, not 100% tested in production.