Datasheet

Description M41T93
10/56 DocID12615 Rev 8
Figure 5. Hardware hookup
1. Open drain output
2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
Figure 6. Data and clock timing
Note: Supports SPI mode 0 (CPOL = 0, CPHA = 0) only.
AI11822
V
CC
Reset Input
(ST6, ST7, ST9, ST10, Others)
SCL
(2)
SPI Interface with
(CPOL = 0, CPHA = 0)
SDI
SDO
CS
32KHz CLKIN
XO
XI
M41T93
MCU
V
SS
V
BAT
IRQ/FT/OUT
(1)
RST
(1)
SDI
SQW
SDO
SCL
V
CC
INT
E
V
CC
Table 2. Function table
Mode E SCL SDI SDO
Disable reset H Input disabled Input disabled High Z
WRITE L
Data bit latch High Z
READ L
X Next data bit shift
(1)
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
AI04630
AI04631
AI04632
SCL
MSB
LSB
CPHA = 0
SDI
CPOL = 0,
MSB
LSB
SDO