M41T93 Serial SPI bus real-time clock (RTC) with battery switchover Datasheet - production data Programmable 8-bit counter/timer 7 bytes of battery-backed user SRAM Battery low flag Low operating current of 80 μA QFN16, 4 mm x 4 mm Oscillator stop detection Battery or supercapacitor backup 18 Operating temperature of –40 °C to +85 °C Package options include a 16-lead QFN and an 18-lead embedded crystal SOIC 1 SOX18, 11.61 x 7.
Contents M41T93 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 2 3 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.1 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.3 Serial clock (SCL) . . . . .
M41T93 Contents 3.9 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.12 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.13 Oscillator fail interrupt enable .
List of tables M41T93 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 4/56 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T93 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QFN16 connections . . . . . . . . .
Description 1 M41T93 Description The M41T93 is a low-power serial SPI bus real-time clock (RTC) with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the SOX18 package). Eight bytes of the register map are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions.
M41T93 Description Figure 1. Logic diagram VBAT VCC XI(1) SQW(2) XO(1) IRQ/OUT/FT(3) SDI RST(3) SCL SDO E VSS AI11818 1. For QFN16 package only 2. Defaults to 32 KHz on power-up 3. Open drain Table 1.
Description M41T93 RST(1) 1 NC 2 XO XI VCC E Figure 2. QFN16 connections 16 15 14 13 12 SDO 11 IRQ/FT/OUT(1) M41T93 SQW(2) 4 9 SDI 5 6 7 8 NC SCL NC 10 VSS 3 VBAT NC AI11819 1. Open drain output 2. Defaults to 32 KHz on power-up Figure 3. SOX18 connections NC (1) NF (1) NF NC (2) RST DU(3) SQW(4) VBAT VSS 1 2 3 4 5 6 7 8 9 M41T93 18 17 16 15 14 13 12 11 10 NC NF(1) (1) NF VCC E SDO (2) IRQ/FT/OUT SCL SDI AI11820 1. NF pins must be tied to VSS.
M41T93 Description Figure 4. Block diagram REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT XI 32KHz OSCILLATOR XO CRYSTAL OFIE A1IE ALARM1 ALARM2 E IRQ/FT/OUT(1) WATCHDOG SDI SPI INTERFACE SCL FT FREQUENCY TEST SDO WRITE PROTECT VCC < VRST(2) OUT OUTPUT DRIVER TIE 8-BIT COUNTER SQWE SQUARE WAVE SQW 8 BITS OF OTP USER SRAM (7 Bytes) INTERNAL POWER VCC VBAT VRST/VSO(2) COMPARE trec TIMER RST(1) AI11821 1. Open drain output 2. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.
Description M41T93 Figure 5. Hardware hookup VCC MCU (ST6, ST7, ST9, ST10, Others) M41T93 VCC VCC (1) XI INT IRQ/FT/OUT (1) RST Reset Input XO SCL SCL VBAT SDO SDI SDI SDO VSS (2) SPI Interface with (CPOL = 0, CPHA = 0) CS E 32KHz CLKIN SQW AI11822 1. Open drain output 2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU. Table 2.
M41T93 Description 1.1 SPI signal description 1.1.1 Serial data output (SDO) The output pin is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. 1.1.2 Serial data input (SDI) The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. 1.1.
Operation 2 M41T93 Operation The M41T93 clock operates as a slave device on the SPI serial bus. It is accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, SDO, and E (see Table 1 on page 7 and Figure 5 on page 10). The device is selected when the chip enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip.
M41T93 Operation By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.” The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T93) device.
Operation M41T93 Figure 7. READ mode sequence E 0 3 2 1 5 4 7 6 9 8 12 13 14 15 16 17 22 SCL 7 BIT ADDRESS W/R BIT SDI 7 6 5 4 3 2 1 0 MSB SDO DATA OUT (BYTE 1) 7 HIGH IMPEDANCE 6 5 4 3 2 DATA OUT (BYTE 2) 1 0 7 MSB MSB 6 5 4 3 2 1 0 AI04635 Figure 8.
M41T93 2.3 Operation Data retention and battery switchover (VSO = VRST) Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life (see Figure 22 on page 47). At this time the clock registers and user RAM will be maintained by the attached battery supply. When it is powered back up, the device switches back from battery to VCC at VSO + hysteresis.
Clock operation 3 M41T93 Clock operation The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 3 on page 20) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format.
M41T93 3.1 Clock operation Clock data coherency In order to synchronize the data during reads and writes of the real-time clock device, a set of buffer transfer registers resides between the SPI serial interface on the user side, and the clock/calendar counters in the part. While the read/write data is transferred in and out of the device one bit at a time to the user, the transfers between the buffer registers and counters occur such that all the bits are copied simultaneously.
Clock operation 3.1.2 M41T93 Accessing the device The M41T93 is comprised of 32 addresses which provide access to registers for time and date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave and NVRAM. The clock and alarm parameters are in binary coded decimal (BCD) format. The calibration, timer, watchdog, and squarewave parameters are in a binary format.
M41T93 3.2.1 Clock operation Power-down time stamp Some applications may need to determine the amount of time spent in backup mode. That can be calculated if the time of power-down and the time of power-up are known. The latter is straightforward to obtain. But the time of power-down is only available if an access occurred just prior to power-down.
Clock operation M41T93 Table 3. Clock/control register map (32 bytes) Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h ST 0 CB1 0 0 0 OUT OFIE A1IE RPT14 RPT13 RPT12 RPT11 WDF TE 12h ACS 13h 14h 15h 16h 17h 18h 19h1Fh RS3 0 RPT24 RPT23 RPT22 RPT21 D6 D5 D4 D3 D2 D1 D0 0.1 seconds 0.
M41T93 3.3 Clock operation Real-time clock accuracy The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see Figure 11 on page 26).
Clock operation 3.4 M41T93 Clock calibration The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25 °C. The M41T93 design provides the following two methods for clock error correction. 3.4.1 Digital calibration (periodic counter correction) This method employs the use of periodic counter correction by adjusting the ratio of the 100 Hz divider stage to the 512 Hz divider stage.
M41T93 Clock operation the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin. Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation.
Clock operation M41T93 Table 4.
M41T93 3.4.2 Clock operation Analog calibration (programmable load capacitance) A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. As discussed in Section 3.4.1, the 512 Hz frequency test output can be used to determine the amount of frequency error in the oscillator. Changes in the analog calibration value will affect the frequency test output, thus the user can immediately see the effects of these changes (see Section 3.
Clock operation M41T93 As shown in Figure 12, the relationship between oscillator speed and load capacitance is not linear. When operating on the left end of the curve, small changes in load capacitance have more effect than when operating on the right end of the curve. For example, at –15 pF, a 3 pF reduction to –18 pF should result in the part running about 30 ppm faster (from +65 ppm to +95 ppm).
M41T93 Clock operation The on-chip capacitance can be calculated as follows: CLOAD = 12.5 + [ACS:(AC6:AC0 value, decimal)] ● 0.125 pF where ACS is the sign. Examples: ACAL (addr 12h) = 0 ➔ CLOAD = 12.5 pF ACAL = 10111100b ➔ CLOAD = 5 pF ACAL = 00010100b ➔ CLOAD = 15 pF With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of 3.5 pF load capacitance as shown on the bottom row of Table 5.
Clock operation M41T93 Figure 12. Clock accuracy vs. on-chip load capacitors 100.0 XI XO PPM ADJUSTMENT 80.0 Crystal Oscillator 60.0 CXI CXO 40.0 CLOAD = 20.0 CXI * CXO CXI + CXO On-Chip FASTER DECREASING LOAD CAP. 0.0 INCREASING LOAD CAP. SLOWER -20.0 OFFSET TO CXI, CXO (pF) NET EQUIV. LOAD CAP., C LOAD, (pF) Analog Calibration Value, AC, register 0x12 28/56 -18.0 -15.0 3.5 5.0 0xC8 0xBC -10.0 -5.0 0.0 5.0 7.5 10 12.5 15 0xA8 0x94 0x00 0x14 9.75 17.
M41T93 Clock operation Two methods are available for ascertaining how much calibration a given M41T93 may require: The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure.
Clock operation M41T93 Figure 14. Crystal isolation example Crystal Local Grounding Plane (Layer 2) XI XO VSS AI11814 Note: The substrate pad should be tied to VSS. 3.5 Setting the alarm clock registers Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings. Either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second.
M41T93 3.6 Clock operation Optional second programmable alarm When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. When the alarm 2 condition is met, the AF2 bit will be set. Reading the flags register (0Fh) will clear it.
Clock operation M41T93 specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog interrupt. Watchdog, address 09h D7 D6 D5 D4 D3 D2 D1 D0 OFIE BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 The watchdog timer is reset by writing to the watchdog register. The time-out period then starts over. Watchdog interrupt On the M41T93, provided that the necessary configuration bits are set, the IRQ/FT/OUT output will be asserted when the watchdog times out (see Section 3.
M41T93 Clock operation without need of software clearing any bits. The TF bit will still be set each time the timer reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing the TF bit has no effect on the output in this mode. While writes to the timer countdown register (10h) control the reload value, reads of this register return the current countdown timer value. Table 7.
Clock operation 3.8.2 M41T93 Timer flag (TF) At the end of a timer countdown, when the timer reloads, TF is set to logic 1. Regardless of the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading. If both timer and alarm interrupts are used in the application, the source of the interrupt can be determined by reading the flag bits. Refer to Section 3.14 for more information on the interaction of these bits. The TF bit is cleared by reading the flags register.
M41T93 3.9 Clock operation Square wave output The M41T93 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 10. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
Clock operation 3.10 M41T93 Battery low warning The M41T93 automatically checks the battery each time VCC powers up and each time the clock rolls over at midnight. VBAT is compared to VBL (approximately 2.5 V), then the battery low (BL) bit, D4 of flags register 0Fh, is set if the battery voltage is found to be less than VBL. Similarly, if VBAT is greater than VBL, the BL bit is cleared during battery check. The BL bit retains its state until the next battery check occurs.
M41T93 Clock operation The M41T93 only checks the battery when powered by VCC. It does not check the battery while in backup mode. Thus, users are advised that during long periods in backup mode, the battery can drop to a level at which timekeeping may fail or data becomes corrupted. If, at power-up, a battery low is indicated, data integrity should be verified.
Clock operation 3.12 M41T93 Oscillator fail detection If the oscillator fail (OF) bit is internally set to a 1, this indicates that the oscillator has either stopped, or was stopped for some period of time. This bit can be used to judge the validity of the clock and date data. This bit will be set to 1 any time the oscillator stops. In the event the OF bit is found to be set to 1 at any time other than the initial power-up, the STOP bit (ST) should be written to a 1, then immediately reset to 0.
M41T93 Clock operation Figure 19 shows the various signal sources and controlling bits for the IRQ/FT/OUT output pin. Figure 19.
Clock operation 3.14.1 M41T93 Active mode operation on VCC On VCC, the operation of the output circuit is as shown in Table 11. Table 11. Priority for IRQ/FT/OUT pin when operating on VCC OUT(1) FT(2) A1IE(3) + OFIE(4) + TIE(5) + watchdog(6) running 0 0 x 0 1 x x 1 0 1 x 1 0 Pin 0 Comment When OUT is 0 and FT is not enabled, OUT dominates and none of the interrupt sources have any effect.
M41T93 3.14.2 Clock operation Backup mode In backup mode, the operation of the output circuit is as shown in Table 12. Table 12. Priority for IRQ/FT/OUT pin when operating in backup mode OUT(1) ABE(2) A1IE(3) + OFIE(4) Pin Comment x 0 x 1 When ABE is 0, the pin is 1 regardless of OUT or the interrupt sources. 1 x 0 1 When OUT is 1 and no interrupts are enabled, the pin is 1. (A1IE and OFIE are the only interrupts applicable in this mode).
Clock operation 3.15 M41T93 Initial power-on defaults Upon initial application of power to the device, the register bits will initially power-on in the state indicated in Table 13 and Table 14. Table 13. Initial power-on default values (part 1) Condition(1) ST Initial power-up Subsequent power-up(3)(4) CB1 CB0 OUT FT DCS Digital Analog OFIE Watchdog(2) A1IE calib. calib. SQWE ABE ACS 0 0 0 1 0 0 0 0 0 0 0 1 0 UC UC UC UC 0 UC UC UC UC 0 UC UC UC 1.
M41T93 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 15.
DC and AC parameters 5 M41T93 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 16.
M41T93 DC and AC parameters Table 18. DC characteristics Sym VCC Test condition(1) Min Operating voltage (S) –40 to 85 °C Operating voltage (R) Parameter Typ Max Unit 3.00 5.50 V –40 to 85 °C 2.70 5.50 V 2.38 Operating voltage (Z) –40 to 85 °C 5.50 V ILI Input leakage current ±1 μA ILO Output leakage current 0 V VIN VCC 0 V VOUT VCC ±1 μA fSCL = 2 MHz 0.5 mA ICC1 Supply current SCL = 0.1VCC/0.9VCC SDO = open fSCL = 5 MHz 1.0 mA fSCL = 10 MHz 2.
DC and AC parameters M41T93 Figure 21. ICC2 vs. temperature 10.000 9.000 8.000 Icc2 (µA) 7.000 (3.0V) (5.0V) 6.000 5.000 4.000 3.000 2.000 -40 -20 0 20 40 60 80 Temperature (°C) ai 13909 Table 19. Crystal electrical characteristics Parameter(1)(2) Symbol Min Typ 32.768 fO Resonant frequency - RS Series resistance - CL Load capacitance - Max Units kHz 65(3) k 12.5 pF 1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145 (1.
M41T93 DC and AC parameters Figure 22. Power down/up mode AC waveforms VCC VSO tPD trec SCL SDI DON'T CARE AI11839 Table 21. Power down/up trip points DC characteristics Parameter(1)(2) Sym VRST VSO trec Reset threshold voltage Min Typ Max Unit S 2.85 2.93 3.0 V R 2.55 2.63 2.7 V Z 2.25 2.32 2.
DC and AC parameters M41T93 Figure 23. Input timing requirements tEHEL E tCHEL tELCH tCHEH tEHCH SCL tDVCH tCHCL tCHDX tCLCH MSB IN SDI HIGH IMPEDANCE SDO LSB IN tDLDH tDHDL AI12295 Figure 24. Output timing requirements E tCH SCL tCLQV tCL tEHQZ tCLQX SDO LSB OUT MSB OUT tQLQH tQHQL SDI ADDR.
M41T93 DC and AC parameters Table 22. AC characteristics Sym Parameter(1) VCC < 2.7 V VCC 2.7 V Min Max Min Max D.C. 5 D.C.
Package mechanical data 6 M41T93 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
M41T93 Package mechanical data Figure 25. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline D E A3 A A1 ddd C e b L K 1 (2) 2 E2 Ch 3 K D2 QFN16-A2 1. Drawing is not to scale 2. Substrate pad should be tied to VSS Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data mm inches Sym Typ Min Max Typ Min Max A 0.90 0.80 1.00 0.035 0.032 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 – – 0.008 – – b 0.30 0.
Package mechanical data M41T93 Figure 26. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint 2.70 0.70 0.20 (2) 4.50 2.70 0.35 0.325 0.65 AI11815 1. Dimensions shown are in millimeters (mm) 2. Substrate pad should be tied to VSS Figure 27. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data 6.0 ± 0.2 3.2 VSOJ20 SMT CRYSTAL 1.5 7.0 ± 0.3 13 14 16 XO 15 XI 1 3.9 2 3 ST QFN16 4 3.9 AI11816 Note: 52/56 Dimensions shown are in millimeters (mm).
M41T93 Package mechanical data Figure 28. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal D 9 h x 45° 1 C E 10 H 18 A2 A B A1 e ddd A1 L SO-J Note: Drawing is not to scale. Table 24. SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data mm inches Sym Typ Min Max Typ Min Max A – 2.44 2.69 – 0.096 0.106 A1 – 0.15 0.31 – 0.006 0.012 A2 – 2.29 2.39 – 0.090 0.094 B – 0.41 0.51 – 0.016 0.020 C – 0.20 0.31 – 0.008 0.
Part numbering 7 M41T93 Part numbering Table 25. Ordering information Example: M41T 93 S QA 6 F Device family M41T Device type 93 Operating voltage S = VCC = 3.00 to 5.5 V R = VCC = 2.70 to 5.5 V Z = VCC = 2.38 to 5.5 V Package QA = QFN16 (4 mm x 4 mm) MY(1) = SOX18 Temperature range 6 = –40 °C to +85 °C Shipping method F = ECOPACK® package, tape & reel 1. The SOX18 package includes an embedded 32,768 Hz crystal.
M41T93 8 Revision history Revision history Table 26. Document revision history Date Revision 12-Oct-2011 6 Updated Features, title, Section 3.1: Clock data coherency, Section 3.2: Halt bit (HT) operation; added Figure 9, added footnote 2 to Table 25: Ordering information. 7 Updated Features bullet concerning accuracy Added footnote 2 within Figure 4 Updated Figure 6 Updated Section 2 and 2.2 Updated Section 3, 3.3, 3.4.1, 3.4.2, and Section 3.5 Updated Figure 13 Updated Section 3.
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