Datasheet

DocID12615 Rev 8 31/56
M41T93 Clock operation
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3.6 Optional second programmable alarm
When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h
through 18h provide control for a second programmable alarm which operates in the same
manner as the alarm function described above. When the alarm 2 condition is met, the AF2
bit will be set. Reading the flags register (0Fh) will clear it. There is no IRQ2 interrupt output
on the M41T93, so no external event can be directly triggered by the alarm 2 function, but
the AF2 bit can be polled to initiate a response.
The AL2E bit defaults on initial power-up to a logic 0 (alarm 2 disabled). In this mode, the
five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of
non-volatile SRAM.
Figure 15. Backup mode alarm waveform
Note: ABE and A1IE bits = 1.
3.7 Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,
and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the
V
CC
IRQ/FT/OUT
AF1 bit in
flags register
HIGH-Z
V
SO
V
PFD
trec
AI11824
Table 6. Alarm repeat modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting
1 1 1 1 1 Once per second
1 1 1 1 0 Once per minute
1 1 1 0 0 Once per hour
1 1 0 0 0 Once per day
1 0 0 0 0 Once per month
0 0 0 0 0 Once per year