Datasheet

DocID12615 Rev 8 7/56
M41T93 Description
56
Figure 1. Logic diagram
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Open drain
Table 1. Signal names
Symbol Description
XI
(1)
1. For QFN16 package only
32 KHz oscillator input
XO
(1)
32 KHz oscillator output
IRQ/FT/OUT Interrupt/frequency test/output driver (open drain)
SQW
(2)
2. Defaults to 32 KHz on power-up
32 KHz programmable square wave output
RST Power-on reset output (open drain)
E Chip enable
SDI Serial data address input
SDO Serial data address output
SCL Serial clock input
V
BAT
Battery supply voltage (tie V
BAT
to V
SS
if no battery is connected)
DU
(3)
3. Do not use (must be tied to V
CC
)
Do not use
V
CC
Supply voltage
V
SS
Ground
SDI
V
CC
V
SS
V
BAT
SCL
RST
(3)
E
IRQ/OUT/FT
(3)
SQW
(2)
SDO
XI
(1)
XO
(1)
AI11818