Datasheet

Clock operation M41T93

38/56 DocID12615 Rev 8

3.12 Oscillator fail detection

If the oscillator fail (OF) bit is internally set to a 1, this indicates that the oscillator has either

stopped, or was stopped for some period of time. This bit can be used to judge the validity of

the clock and date data. This bit will be set to 1 any time the oscillator stops.

In the event the OF bit is found to be set to 1 at any time other than the initial power-up, the

STOP bit (ST) should be written to a 1, then immediately reset to 0. This will restart the

oscillator. This is called kick-starting, and it injects extra current into the oscillator for a short

period of time to help it get started.

The following conditions can cause the OF bit to be set:

 The voltage present on V

or battery is insufficient to support oscillation.

 The ST bit is set to 1.

 External interference of the crystal

 The first time power is applied (defaults to a 1 on power-up).

Note: If the OF bit cannot be written to 0 four seconds after the initial power-up, the user should

perform the kick-start of the oscillator as noted above. Kick-starting should only be

performed when the OF bit is set.

For the M41T93, if the oscillator fail interrupt enable bit (OFIE) is set to a 1, the IRQ/FT/OUT

pin will also be asserted (see Section 3.13 and Section 3.14 for additional conditions which

apply). The IRQ/FT/OUT output is de-asserted by resetting the OF bit to 0, NOT by reading

the flags register. The OF bit will remain a 1 until written to 0. Reading the flags register has

no effect on OF.

The oscillator must start and have run for at least 4 seconds before attempting to reset the

OF bit to 0.

The oscillator fail detect circuit functions during backup mode. If a triggering event occurs to

disrupt the oscillator during a power-down condition, the OF bit will be set accordingly.

3.13 Oscillator fail interrupt enable

With the OFIE bit set, the OF bit will cause the IRQ/FT/OUT output to be asserted (see

Section 3.14.1 and 3.14.2 for additional conditions that apply). The IRQ/FT/OUT output is

cleared by resetting the OF bit to 0 (NOT by reading the flags register). Clearing the OFIE

bit will also cause the IRQ/FT/OUT output to de-assert, but if OFIE is subsequently set prior

to clearing OF, the IRQ/FT/OUT output will assert immediately upon setting OFIE. Clearing

the OF bit is necessary to prevent such an inadvertent interrupt.

If the alarm in backup enable bit, ABE, is set (along with OFIE), the oscillator fail detect will

cause an interrupt in the IRQ/FT/OUT pin during backup mode. For additional information

on this, refer to Section 3.14.2.

3.14 IRQ/FT/OUT pin, frequency test, interrupts and the OUT bit

Four interrupt sources, the frequency test function, and the discrete output bit OUT all share

the IRQ/FT/OUT pin. Priority is built into the part such that some functions dominate others.

Additionally, the priority depends on configuration bits such as OUT and ABE, and on

whether the part is operating on V

or is in the backup mode. This pin is an open drain

output and requires an external pull-up resistor.