Datasheet

Clock operation M41T93
34/56 DocID12615 Rev 8
3.8.2 Timer flag (TF)
At the end of a timer countdown, when the timer reloads, TF is set to logic 1. Regardless of
the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading.
If both timer and alarm interrupts are used in the application, the source of the interrupt can
be determined by reading the flag bits. Refer to Section 3.14 for more information on the
interaction of these bits. The TF bit is cleared by reading the flags register. This will de-
assert an interrupt output due to the timer.
3.8.3 Timer interrupt enable (TIE)
In normal interrupt mode (TI/TP = 0), when TF is asserted, the interrupt output is asserted (if
TIE = 1). To de-assert the interrupt, the TF bit or the TIE bit must be reset. Disabling the
interrupt by clearing the TIE bit will de-assert the output, but does not clear the TF bit. Thus,
if TIE is re-enabled prior to clearing TF, the interrupt will assert immediately.
3.8.4 Timer enable (TE)
 TE = 0
When TE = 0, or when the timer register (10h) is set to 0, the timer is disabled.
 TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin counting from the same value as when it was disabled.
3.8.5 TD1/0
These are the timer source clock frequency selection bits (see Table 9). These bits
determine the source clock for the countdown timer (see Table 7). When not in use, the TD1
and TD0 bits should be set to 11 (1/60 Hz) for power saving.
Note: Writing to the timer register will not reset the TF bit nor clear the interrupt.
Table 9. Timer source clock frequency selection (244.1 μs to 4.25 hrs)
TD1 TD0 Timer source clock frequency (Hz)
0 0 4096 (244.1 μs)
0 1 64 (15.6 ms)
1 0 1 (1 s)
1 1 1/60 (60 s)