Datasheet

Operation M41T93
12/56 DocID12615 Rev 8
2 Operation
The M41T93 clock operates as a slave device on the SPI serial bus. It is accessed by a
simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, SDO,
and E (see Table 1 on page 7 and Figure 5 on page 10). The device is selected when the
chip enable input (E) is held low. All instructions, addresses and data are shifted serially in
and out of the chip. The most significant bit is presented first, with the data input (SDI)
sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low. The 32
bytes contained in the device can then be accessed sequentially in the following order:
 1
st
byte: tenths/hundredths of a second register
 2
nd
byte: seconds register
 3
rd
byte: minutes register
 4
th
byte: century/hours register
 5
th
byte: day register
 6
th
byte: date register
 7
th
byte: month register
 8
th
byte: year register
 9
th
byte: digital calibration register
 10
th
byte: watchdog register
 11
th
- 15
th
bytes: alarm 1 registers
 16
th
byte: flags register
 17
th
byte: timer value register
 18
th
byte: timer control register
 19
th
byte: analog calibration register
 20
th
byte: square wave register
 21
st
- 25
th
bytes: alarm 2 registers
 26
th
- 32
nd
bytes: user RAM
The M41T93 clock continually monitors V
CC
for an out-of tolerance condition. Should V
CC
fall below V
RST
, the device terminates any access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out-of-tolerance system.
The power input will also be switched from the V
CC
pin to the external battery when V
CC
falls below the battery back-up switchover voltage (V
SO
= V
RST
). At this time the clock
registers will be maintained by the battery supply. As system power returns and V
CC
rises
above V
SO
, the battery is disconnected, and the power supply is switched to external V
CC
.
The device remains write protected until t
REC
seconds elapse after V
CC
rises above
V
PFD
(min). For more information on battery storage life refer to application note AN1012.
2.1 SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication
between different ICs. It consists of four signal lines: serial data input (SDI), serial data
output (SDO), serial clock (SCL) and a chip enable (E).