Datasheet

DocID12615 Rev 8 33/56
M41T93 Clock operation
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without need of software clearing any bits. The TF bit will still be set each time the timer
reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing
the TF bit has no effect on the output in this mode.
While writes to the timer countdown register (10h) control the reload value, reads of this
register return the current countdown timer value.
When the timer is in the free-running mode, with a value of n programmed into the timer
countdown value, the output will nominally be low for one cycle of the specified clock source
and high for n-1 cycles with an overal period of n cycles. Thus, the countdown period is
n/source clock frequency.
For the special case of n = 1, as shown in Table 8, when the clock source is 4096 or 64 Hz,
the low time (T
L
) is half the clock period instead of a full clock period.
Figure 16. Timer output waveform in free-running mode (with TI/TP = 1)
Table 7. Timer control register map
Addr D7 D6 D5 D4 D3 D2 D1 D0 Function
0Fh WDF AF1 AF2 BL TF OF 0
(1)
1. Bit positions labeled with 0 should always be written with logic 0.
0
(1)
Flags
10h Timer countdown value
(2)
2. Writing to the timer register will not reset the TF bit nor clear the interrupt.
Timer value
11h TE
TI/TP TIE 0
(1)
0
(1)
0
(1)
TD1 TD0 Timer control
Table 8. Timer interrupt operation in free-running mode (with TI/TP = 1)
Source clock (Hz)
IRQ low time – T
L
(seconds)
(1)
1. IRQ/FT/OUT is asserted coincident with TF going true.
IRQ period – T
IRQ
(seconds)
n = 1
(2)
2. n = loaded countdown timer value (0 < n < 255). The timer is stopped when n = 0.
n > 1 n = 1 n > 1
4096 1/8192 = 122 μs 1/4096 = 244 μs 1/4096 = 244 μs n / 4096
64 1/128 = 7.8 ms 1/64 = 15.6 ms 1/64 = 15.6 ms n / 64
1 1/64 1/64 1 n
1/60 1/64 1/64 1 minute n minutes
T
L
AM03012v1
IRQ/FT/OUT
T
IRQ