M41T82, M41T83 Serial I2C bus real-time clock (RTC) with battery switchover Datasheet - production data Optional 2nd programmable alarm available Square wave output defaults to 32 KHz on power-up (M41T83 only) QFN16 (4 mm x 4 mm) RESET (RST) output Watchdog timer Programmable 8-bit counter/timer 7 bytes of battery-backed user SRAM SO8 (4.90 mm x 3.
Contents M41T82, M41T83 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.
M41T82, M41T83 Contents 3.8.5 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.9 Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.12 Oscillator fail detection . . . .
List of tables M41T82, M41T83 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. 4/64 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T82, M41T83 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 M41T82, M41T83 Description The M41T8x are low-power serial I2C real-time clocks (RTCs) with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the SOX18 package). Eight bytes of the register map (see Table 2 on page 23) are used for the clock/calendar function and are configured in binary-coded decimal (BCD) format.
M41T82, M41T83 Description Figure 1. M41T82 logic diagram VBAT VCC XI XO FT/RST(1) SDA SCL VSS AI11196 1. Open drain Figure 2. M41T83 logic diagram VBAT VCC SQW(2) XI(1) IRQ1/OUT/FT(3) XO(1) SDA RST(3) SCL IRQ2(3) VSS AI11195 1. For QFN16 package only 2. Defaults to 32 KHz on power-up 3.
Description M41T82, M41T83 Table 1.
M41T82, M41T83 Description Figure 3. SO8 (M) connections (M41T82) 1 2 3 4 XI XO VBAT VSS M41T82 8 7 6 5 VCC FT/RST(1) SCL SDA AI11199 1. Open drain output RST(1) 1 NC 2 XO XI VCC NC Figure 4. QFN16 (QA) connections (M41T83) 16 15 14 13 12 IRQ2(1) 11 IRQ1/FT/OUT(1) 10 SCL 9 SDA 4 5 6 7 8 NC SQW(2) NC 3 VSS NC VBAT M41T83 AI11197 1. Open drain output. 2. Defaults to 32 KHz on power-up. Figure 5.
Description M41T82, M41T83 Figure 6. M41T82 block diagram REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT XI 32KHz OSCILLATOR XO CRYSTAL ALARM1 ALARM2 WATCHDOG SDA I2C INTERFACE SCL FT FREQUENCY TEST OUTPUT DRIVER WRITE PROTECT VCC < VRST 8-BIT COUNTER USER SRAM (7 Bytes) INTERNAL POWER VCC VBAT VRST/VSO(1) COMPARE trec TIMER RST (2) AI11812 1. VRST = VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z). 2. Open drain output. Figure 7.
M41T82, M41T83 Description Figure 8. M41T83 block diagram REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT XI CRYSTAL 32KHz OSCILLATOR XO OFIE A1IE ALARM1 A2IE ALARM2 IRQ2(1) IRQ1/FT/OUT(1) WATCHDOG SDA I2C INTERFACE FT FREQUENCY TEST SCL WRITE PROTECT VCC < VRST OUT OUTPUT DRIVER TIE 8-BIT COUNTER SQWE SQUARE WAVE SQW 8 BITS OF OTP USER SRAM (7 Bytes) INTERNAL POWER VCC VBAT VRST/VSO(2) COMPARE trec TIMER RST(1) AI11800 1. Open drain output. 2. VRST = VSO = 2.93 V (S), 2.
Operation 2 M41T82, M41T83 Operation The M41T8x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h).
M41T82, M41T83 2.1 Operation 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high.
Operation 2.1.5 M41T82, M41T83 Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
M41T82, M41T83 Read mode In this mode the master reads the M41T8x slave after setting the slave address (see Figure 13 on page 16). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W = 1). At this point the master transmitter becomes the master receiver.
Operation M41T82, M41T83 R/W DATA n+1 ACK DATA n ACK BUS ACTIVITY: S ACK ACK WORD ADDRESS (An) ACK S START SDA LINE R/W BUS ACTIVITY: MASTER START Figure 13. Read mode sequence SLAVE ADDRESS STOP SLAVE ADDRESS P NO ACK DATA n+X AI00899 STOP DATA n+X SLAVE ADDRESS 16/64 ACK BUS ACTIVITY: DATA n+1 ACK DATA n P NO ACK R/W S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 14.
M41T82, M41T83 2.3 Operation Write mode In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is shown in Figure 15. Following the START condition and slave address, a logic 0 (R/W = 0) is placed on the bus and indicates to the addressed device that word address “An” will follow and is to be written to the on-chip address pointer.
Operation 2.4 M41T82, M41T83 Data retention and battery switchover (VSO = VRST) Once VCC falls below the switchover voltage (VSO = VRST), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched from VCC to VBAT when VCC drops below VRST (see Figure 28 on page 54).
M41T82, M41T83 3 Clock operation Clock operation The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format.
Clock operation 3.1 M41T82, M41T83 Clock data coherency In order to synchronize the data during reads and writes of the real-time clock device, a set of buffer transfer registers resides between the I2C serial interface on the user side, and the clock/calendar counters in the part. While the read/write data is transferred in and out of the device one bit at a time to the user, the transfers between the buffer registers and counters occur such that all the bits are copied simultaneously.
M41T82, M41T83 3.1.2 Clock operation Accessing the device The M41T82/83 is comprised of 32 addresses which provide access to registers for time and date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave (M41T83 only) and NVRAM. The clock and alarm parameters are in binary coded decimal (BCD) format. The calibration, timer, watchdog, and squarewave parameters are in a binary format.
Clock operation 3.2.1 M41T82, M41T83 Power-down time-stamp Some applications may need to determine the amount of time spent in backup mode. That can be calculated if the time of power-down and the time of power-up are known. The latter is straightforward to obtain. But the time of power-down is only available if an access occurred just prior to power-down.
M41T82, M41T83 Clock operation Table 2. M41T82 clock/control register map (32 bytes)(1) Function/range BCD Addr D7 00h D6 D5 D4 D3 D2 0.1 seconds D1 format D0 0.
Clock operation M41T82, M41T83 Table 3.
M41T82, M41T83 Clock operation Table 4. M41T83 clock/control register map (32 bytes)(1) Addr D7 00h D6 D5 D4 D3 D2 0.1 seconds D1 D0 Function/range BCD format 0.
Clock operation M41T82, M41T83 Table 5.
M41T82, M41T83 3.3 Clock operation Real-time clock accuracy The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see Figure 18 on page 32).
Clock operation 3.4 M41T82, M41T83 Clock calibration The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25 °C. The M41T8x design provides the following two methods for clock error correction. 3.4.
M41T82, M41T83 Clock operation the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin. Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation.
Clock operation M41T82, M41T83 Table 6.
M41T82, M41T83 3.4.2 Clock operation Analog calibration (programmable load capacitance) A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. As discussed in Section 3.4.1, the 512 Hz frequency test output can be used to determine the amount of frequency error in the oscillator.
Clock operation M41T82, M41T83 As shown in Figure 19, the relationship between oscillator speed and load capacitance is not linear. When operating on the left end of the curve, small changes in load capacitance have more effect than when operating on the right end of the curve. For example, at –15 pF, a 3 pF reduction to –18 pF should result in the part running about 30 ppm faster (from +65 ppm to +95 ppm).
M41T82, M41T83 Clock operation The on-chip capacitance can be calculated as follows: CLOAD = 12.5 + [ACS:(AC6:AC0 value, decimal)] ● 0.125 pF where ACS is the sign. Examples: ACAL (addr 12h) = 0 ➔ CLOAD = 12.5 pF ACAL = 10111100b ➔ CLOAD = 5 pF ACAL = 00010100b ➔ CLOAD = 15 pF With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of 3.5 pF load capacitance as shown on the bottom row of Table 7.
Clock operation M41T82, M41T83 Figure 19. Clock accuracy vs. on-chip load capacitance 100.0 XI XO PPM ADJUSTMENT 80.0 Crystal Oscillator 60.0 CXI CXO 40.0 CLOAD = 20.0 CXI * CXO CXI + CXO On-Chip FASTER DECREASING LOAD CAP. INCREASING LOAD CAP. 0.0 SLOWER -20.0 OFFSET TO CXI, CXO (pF) NET EQUIV. LOAD CAP., C LOAD, (pF) Analog Calibration Value, AC, register 0x12 34/64 -18.0 -15.0 3.5 5.0 0xC8 0xBC -10.0 -5.0 0.0 5.0 9.75 7.5 10 12.5 15 17.
M41T82, M41T83 Clock operation Two methods are available for ascertaining how much calibration a given M41T8x may require: The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure.
Clock operation M41T82, M41T83 Figure 21. Crystal isolation example Crystal Local Grounding Plane (Layer 2) XI XO VSS AI11814 1. Substrate pad should be tied to VSS. 3.5 Setting the alarm clock registers Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPTx5–RPTx1 (x = 1 for alarm 1 or 2 for alarm 2), the alarm flag, AFx, is set.
M41T82, M41T83 3.6 Clock operation Optional second programmable alarm and user SRAM When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described in Section 3.5. The AL2E bit defaults on initial power-up to a logic 0 (alarm 2 disabled). In this mode, the five alarm 2 bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of user SRAM.
Clock operation M41T82, M41T83 A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but not deassert the IRQ1/FT/OUT output. The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. Table 9. Watchdog register 3.8 Addr D7 D6 D5 D4 D3 D2 D1 D0 Function 09h OFIE BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 8-bit (countdown) timer The timer value register is an 8-bit binary countdown timer.
M41T82, M41T83 Clock operation Table 10. Timer control register map(1) Addr D7 D6 D5 D4 D3 0Fh WDF AF1 AF2 BL TF D2 D1 D0 Function OF 0 0 Flags (2) 10h Timer countdown value 11h TE TI/TP TIE 0 0 Timer value 0 TD1 TD0 Timer control 1. Bit positions labeled with 0 should always be written with logic 0. 2. Writing to the timer register will not reset the TF bit nor clear the interrupt.
Clock operation 3.8.2 M41T82, M41T83 Timer flag (TF) At the end of a timer countdown, when the timer reloads, TF is set to logic '1.' Regardless of the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading. If both timer and alarm interrupts are used in the application, the source of the interrupt can be determined by reading the flag bits. Refer to Section 3.14 for more information on the interaction of these bits. The TF bit is cleared by reading the flags register.
M41T82, M41T83 3.9 Clock operation Square wave output (M41T83 only) The M41T83 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 13. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
Clock operation 3.10 M41T82, M41T83 Battery low warning The M41T8x automatically checks the battery each time VCC powers up and each time the clock rolls over at midnight. VBAT is compared to VBL (approximately 2.5 V), then the battery low (BL) bit, D4 of flags register 0Fh, is set if the battery voltage is found to be less than VBL. Similarly, if VBAT is greater than VBL, the BL bit is cleared during battery check. The BL bit retains its state until the next battery check occurs.
M41T82, M41T83 Clock operation The M41T8x only checks the battery when powered by VCC. It does not check the battery while in backup mode. Thus, users are advised that during long periods in backup mode, the battery can drop to a level at which timekeeping may fail or data becomes corrupted. If, at power-up, a battery low is indicated, data integrity should be verified.
Clock operation 3.12 M41T82, M41T83 Oscillator fail detection If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time. This bit can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops.
M41T82, M41T83 Clock operation Figure 25. IRQ1/FT/OUT output pin circuit TIMER TE reload TF TI/TP TIE OUT FT ABE Write OF to 0 to clear Read FLAGS register to clear IRQ1/OUT/FT LOGIC IRQ1/OUT/FT A1IE OFIE TIE w-dog running OF OFIE AF1 AI1E WDF Write watchdog register to clear PRE Q WDOG AM03013v1 The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the primary interrupt sources.
Clock operation 3.14.1 M41T82, M41T83 Active mode operation on VCC On VCC, the operation of the output circuit is as shown in Table 14. Table 14. Priority for IRQ1/FT/OUT pin when operating on VCC OUT(1) FT(2) A1IE(3) + OFIE(4) + TIE(5) + watchdog(6) running 0 0 x 0 1 x x 1 0 1 x 1 0 Pin 0 Comment When OUT is 0 and FT is not enabled, OUT dominates and none of the interrupt sources have any effect.
M41T82, M41T83 3.14.2 Clock operation Backup mode In backup mode, the operation of the output circuit is as shown in Table 15. Table 15. Priority for IRQ1/FT/OUT pin when operating in backup mode OUT(1) ABE(2) A1IE(3) + OFIE(4) Pin Comment x 0 x 1 When ABE is 0, the pin is 1 regardless of OUT or the interrupt sources. 1 x 0 1 When OUT is 1 and no interrupts are enabled, the pin is 1. (A1IE and OFIE are the only interrupts applicable in this mode).
Clock operation 3.15 M41T82, M41T83 FT/RST pin, frequency test and reset output pin (M41T82 only) On the M41T82, the 512 Hz frequency test signal and the reset output share the same pin, FT/RST. When the FT bit (bit 6 of register 08h) is a 1, the 512 Hz test signal is activated on the pin. With FT a 0 and VCC good (above VRST), the output will be high. If the 512 Hz is enabled when VCC fails, the FT bit will be cleared and the output will go low to assert reset.
M41T82, M41T83 3.17 Clock operation OTP bit operation (M41T83 in SOX18 package only) Using the factory-supplied analog calibration value When the OTP (one time programmable) bit is set to a 1, the factory calibration value in the internal OTP register will be transferred to the analog calibration register (12h) and is “read only.” The OTP value is programmed by the manufacturer, and will contain the value necessary to achieve typically ±5 ppm (a) at room temperature (VCC only) after two SMT reflows.
Maximum ratings 4 M41T82, M41T83 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 18.
M41T82, M41T83 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 19.
DC and AC parameters M41T82, M41T83 Table 21. DC characteristics Sym Test condition(1) Min Operating voltage (S) –40 to 85 °C Operating voltage (R) Max Unit 3.00 5.50 V –40 to 85 °C 2.70 5.50 V Operating voltage (Z) –40 to 85 °C 2.38 5.50 V ILI Input leakage current 0V VIN VCC ±1 μA ILO Output leakage current 0V VOUT VCC ±1 μA 150 μA VCC ICC1 Parameter Supply current Typ 5.5 V 125 3.0 V 55 μA 2.5 (Z only) 45 μA 5.5 V 8 3.0 V 6.
M41T82, M41T83 DC and AC parameters Figure 27. ICC2 vs. temperature 10.000 9.000 8.000 Icc2 (µA) 7.000 (3.0V) (5.0V) 6.000 5.000 4.000 3.000 2.000 -40 -20 0 20 40 60 80 Temperature (°C) ai 13909 Table 22. Crystal electrical characteristics Parameter(1)(2) Symbol fO Min Resonant frequency RS Series resistance CL Load capacitance Typ Max 32.768 Units kHz 65(3) 12.5 k pF 1. Externally supplied if using the QFN16 or SO8 package.
DC and AC parameters M41T82, M41T83 Figure 28. Power down/up mode AC waveforms VCC VSO VRST trec SDA, SCL DON'T CARE tRD RST AI00596 Table 24. Power down/up trip points DC characteristics Parameter(1)(2) Sym VRST VSO trec tRD Reset threshold voltage Min Typ Max Unit S 2.85 2.93 3.0 V R 2.55 2.63 2.7 V Z 2.25 2.32 2.38 V Battery backup switchover Hysteresis RST duration after VCC high VCC to reset delay(3) VRST V 25 mV 140 280 2.5 ms μs 1.
M41T82, M41T83 DC and AC parameters Figure 29. Bus timing requirement sequence SDA tBUF tHD:STA tHD:STA tR tF SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR tSU:STO P AI00589 Table 25. AC characteristics Parameter(1) Sym Min Typ Max Units 400 kHz fSCL SCL clock frequency tLOW Clock low period 1.
Package mechanical data 6 M41T82, M41T83 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
M41T82, M41T83 Package mechanical data Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline D E A3 A1 A ddd C e b L 1 2 E2 3 D2 QFN16-A Note: Drawing is not to scale. Table 26. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data mm inches Sym Typ Min Max Typ Min Max A 0.90 0.80 1.00 0.035 0.031 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 – – 0.008 – – b 0.30 0.25 0.35 0.012 0.010 0.014 D 4.00 3.
Package mechanical data M41T82, M41T83 Figure 31. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint 2.70 0.70 0.20 4.50 2.70 0.35 0.325 0.65 Note: AI11815 Dimensions are shown in millimeters (mm). Figure 32. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data 6.0 ± 0.2 3.2 VSOJ20 SMT CRYSTAL 1.5 7.0 ± 0.3 13 14 16 XO 3.9 15 XI 1 2 3 ST QFN16 4 3.9 AI11816 Note: 58/64 Dimensions shown are in millimeters (mm).
M41T82, M41T83 Package mechanical data Figure 33. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline SOX18 Note: Drawing is not to scale. Table 27. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data millimeters inches Symbol Typ Min Max Typ Min Max A 2.57 2.44 2.69 0.101 0.096 0.106 A1 0.23 0.15 0.31 0.009 0.006 0.012 A2 2.34 2.29 2.39 0.092 0.090 0.094 B 0.46 0.41 0.51 0.018 0.016 0.020 c 0.25 0.20 0.
Package mechanical data M41T82, M41T83 Figure 34. SO8 – 8-lead plastic small package outline h x 45° A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A Note: Drawing is not to scale. Table 28. SO8 – 8-lead plastic small outline (150 mils body width), package mech. data mm inches Symbol Typ Min A Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.
M41T82, M41T83 Package mechanical data Figure 35. Carrier tape for QFN16, SOX18, and SO8 packages P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 29. Carrier tape dimensions for QFN16, SOX18, and SO8 packages Package W D QFN16 12.00 0.30 1.50 +0.10/ –0.00 SOX18 24.00 0.30 SO8 12.00 0.30 E P0 P2 F B0 K0 P1 T 1.75 4.00 2.00 5.50 0.10 0.10 0.10 0.05 4.30 0.10 4.30 0.10 1.10 0.10 8.00 0.10 0.30 0.
Part numbering 7 M41T82, M41T83 Part numbering Table 30. Ordering information Example: M41T 83 S QA 6 F Device family M41T Device type 82 (SO8 package only) 83 Operating voltage S = VCC = 3.00 to 5.5 V R = VCC = 2.70 to 5.5 V Z = VCC = 2.38 to 5.5 V Package QA = QFN16 (4 mm x 4 mm) M(1) = SO8 MY(2) = SOX18 Temperature range 6 = –40 °C to 85 °C Shipping method F = ECOPACK® package, tape & reel 1. M41T82 only 2. The SOX18 package includes an embedded 32,768 Hz crystal.
M41T82, M41T83 8 Revision history Revision history Table 31. Document revision history Date Revision Changes 09-Apr-2009 9 Updated Table 1, 2, 4, 6, 10, 11, 21, Figure 20, 28, Section 3, Section 3.4.1, Section 3.4.2, Section 3.5, Section 3.6, Section 3.7, Section 3.8, Section 3.8.2, Section 3.8.3, Section 3.8.4, Section 3.8.5, Section 3.12, Section 3.13, Section 6; added Section 3.8.1, Section 3.14, Section 3.
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