Datasheet

Clock operation M41T82, M41T83
48/64 DocID012578 Rev 16
3.15 FT/RST pin, frequency test and reset output pin (M41T82
only)
On the M41T82, the 512 Hz frequency test signal and the reset output share the same pin,
FT/RST. When the FT bit (bit 6 of register 08h) is a 1, the 512 Hz test signal is activated on
the pin. With FT a 0 and V
CC
good (above V
RST
), the output will be high. If the 512 Hz is
enabled when V
CC
fails, the FT bit will be cleared and the output will go low to assert reset.
At power-up, FT will be 0 leaving the pin functioning as the reset output.
3.16 Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the
state indicated in Table 16 and Table 17.
Table 16. Initial power-on default values (part 1)
Condition
(1)
1. All other control bits power-up in an undetermined state.
ST CB1 CB0 OUT FT
DCS
ACS
Digital
calib.
Analog
calib.
OFIE
(2)
2. M41T83 only
Watch-
dog
(3)
3. BMB0-BMB4, RB0, RB1
A1IE
(2)
SQWE
(2)
ABE
Initial
power-up
00 0 100 0 0 0 0 0 1 0
Subsequent
power-up
(4)(5)
4. With battery backup
5. UC = unchanged
UC UC UC UC 0 UC UC UC UC 0 UC UC UC
Table 17. Initial power-up default values (part 2)
Condition
(1)
1. All other control bits power-up in an undetermined state.
RPT11-
15
HT OF TE
TI/TP
(2)
2. M41T83 only
TIE
(2)
TD1 TD0 RS0 RS1-3
OTP
(2)
A2IE
(2)
RPT21-
25
AL2E
Initial
power-up
01100 01110 0 0 0 0
Subsequent
power-
up
(3)(4)
3. With battery backup
4. UC = unchanged
UC 1 UC 0 UC UC UC UC UC UC UC UC UC UC