Datasheet

DocID012578 Rev 16 33/64

M41T82, M41T83 Clock operation

The on-chip capacitance can be calculated as follows:

LOAD

= 12.5 + [ACS:(AC6:AC0 value, decimal)] ● 0.125 pF

where ACS is the sign.

Examples:

ACAL (addr 12h) = 0 ➔ C

LOAD

= 12.5 pF

ACAL = 10111100b ➔ C

LOAD

= 5 pF

ACAL = 00010100b ➔ C

LOAD

= 15 pF

With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of

3.5 pF load capacitance as shown on the bottom row of Table 7.

Note: These are typical values, and the total load capacitance seen by the crystal will include

approximately 1-2 pF of package and board capacitance in addition to the analog calibration

Any invalid value of analog calibration will result in the default capacitance of 25 pF (for C

and C

Combining the digital adjustment range (–63 to +126 ppm) and analog adjustment range

(–15 to +95 ppm), the approximate overall adjustment range of the M41T82-83’s

timekeeping is –78 to +221 ppm.

Figure 19 represents a typical curve of clock ppm adjustment versus the analog calibration

value. Actual crystals may vary, so users should evaluate the crystals to be used with an

M41T82-83 device before establishing the adjustment values for a given application.