Datasheet

Operation M41T82, M41T83
12/64 DocID012578 Rev 16
2 Operation
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 32 bytes
contained in the device can then be accessed sequentially in the following order:
 1
st
byte: tenths/hundredths of a second register
 2
nd
byte: seconds register
 3
rd
byte: minutes register
 4
th
byte: century/hours register
 5
th
byte: day register
 6
th
byte: date register
 7
th
byte: month register
 8
th
byte: year register
 9
th
byte: digital calibration register
 10
th
byte: watchdog register
 11
th
- 15
th
bytes: alarm 1 registers
 16
th
byte: flags register
 17
th
byte: timer value register
 18
th
byte: timer control register
 19
th
byte: analog calibration register
 20
th
byte: square wave register
 21
st
- 25
th
bytes: alarm 2 registers
 26
th
- 32
nd
bytes: user RAM
The M41T8x clock continually monitors V
CC
for an out-of-tolerance condition. Should V
CC
fall below V
RST
, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out-of-tolerance system. The power input will also
be switched from the V
CC
pin to the battery when V
CC
falls below the battery back-up
switchover voltage (V
SO
= V
RST
). At this time the clock registers will be maintained by the
attached battery supply. As system power returns and V
CC
rises above V
SO
, the battery is
disconnected, and the power supply is switched to external V
CC
.