M41T81S Serial access real-time clock (RTC) with alarms Datasheet − production data Features ■ ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32 KHz crystal oscillator with integrated load capacitance (12.
Contents M41T81S Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T81S Contents 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of tables M41T81S List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. 4/32 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alarm repeat modes . . . . . . . . . . . . . .
M41T81S List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 M41T81S Description The M41T81S is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator (external crystal controlled). Eight bytes of the SRAM are used for the clock/calendar function and are configured in binary-coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/control of alarm, watchdog and square wave functions. Addresses and data are transferred serially via a two line, bidirectional I2C interface.
M41T81S Description Table 1. Signal names (1) XI Oscillator input XO(1) Oscillator output IRQ/OUT/FT/SQW Interrupt / output driver / frequency test / square wave (open drain) SDA Serial data input/output SCL Serial clock input VBAT Battery supply voltage VCC Supply voltage VSS Ground NC(2) No connect NF(2) No function 1. For SO8 package only. 2. NC and NF pins should be tied to VSS. Figure 2.
Description Figure 4. M41T81S Block diagram REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR CRYSTAL OSCILLATOR FAIL CIRCUIT OFIE RTC W/ALARM & CALIBRATION AFE IRQ/FT/OUT/SQW(1) WATCHDOG SDA I2C INTERFACE (2) SQWE SQUARE WAVE SCL WRITE PROTECT FREQUENCY TEST FT OUTPUT DRIVER OUT INTERNAL POWER VCC VBAT VSO COMPARE VPFD AI09163 1. Open drain output 2. Square wave function has the highest priority on IRQ/FT/OUT/SQW output.
M41T81S 2 Operation Operation The M41T81S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/hundredths of a second register 2. Seconds register 3. Minutes register 4. Century/hours register 5. Day register 6. Date register 7. Month register 8. Year register 9. Calibration register 10.
Operation M41T81S The following protocol has been defined: ● Data transfer may be initiated only when the bus is not busy. ● During data transfer, the data line must remain stable whenever the clock line is high. ● Changes in the data line, while the clock line is high, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy Both data and clock lines remain high.
M41T81S Operation case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 5. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 Figure 6.
Operation Note: M41T81S This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41T81S slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9 on page 12). Figure 7.
M41T81S Operation WRITE mode In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is shown in Figure 10 on page 13. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address “An” will follow and is to be written to the on-chip address pointer.
Clock operation 3 M41T81S Clock operation The 20-byte register map (see Table 2: Clock register map on page 15) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: Tenths/hundredths of seconds cannot be written to any value other than “00.
M41T81S Clock operation Table 2. Clock register map Addr D7 D6 D5 0.1 seconds 00h D4 D3 D2 D1 0.
Clock operation M41T81S Calibrating the clock The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +1.9 to –1.1 minutes per month (see Figure 11 on page 17). When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes with temperature.
M41T81S Clock operation The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Figure 11. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 ΔF = K x (T – T )2 O F –80 2 K = –0.036 ppm/°C ± 0.
Clock operation M41T81S When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/SQW pin. Note: If the address pointer is allowed to increment to the flags register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address.
M41T81S Clock operation Table 3. Alarm repeat modes RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting 1 1 1 1 1 Once per second 1 1 1 1 0 Once per minute 1 1 1 0 0 Once per hour 1 1 0 0 0 Once per day 1 0 0 0 0 Once per month 0 0 0 0 0 Once per year Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h.
Clock operation M41T81S Square wave output The M41T81S offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 4. Once the selection of the SQW frequency has been completed, the IRQ/FT/OUT/SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah. Table 4.
M41T81S Clock operation Battery low warning The M41T81S automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V.
Clock operation M41T81S Output driver pin When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low. Note: The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
M41T81S 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6.
DC and AC parameters 5 M41T81S DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7.
M41T81S DC and AC parameters Table 9. Sym DC characteristics Test condition(1) Parameter Min Typ Max Unit ±1 µA 0 V ≤ VIN ≤ VCC ILI Input leakage current ILO Output leakage current ICC1 Supply current 0 V ≤ VOUT ≤ VCC ±1 µA Switch freq = 400 kHz 400 µA SCL = 0 Hz All inputs ≥ VCC – 0.2 V ≤ VSS + 0.2 V 100 µA ICC2 Supply current (standby) VIL Input low voltage –0.3 0.3VCC V VIH Input high voltage 0.7VCC VCC + 0.3 V VOL Output low voltage IOL = 3.0 mA 0.
DC and AC parameters Table 11. M41T81S Power down/up AC characteristics Symbol tPD Parameter(1)(2) SCL and SDA at VIH before power-down Min 0 Typ - Max - Unit nS trec SCL and SDA at VIH after power-up 10 - - µS 1. VCC fall time should not exceed 5 mV/µs. 2. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted). Table 12. Power down/up trip points DC characteristics Parameter(1)(2) Sym VPFD VSO Power-fail deselect Min Typ Max Unit 2.5 2.
M41T81S DC and AC parameters Table 13. AC characteristics Parameter(1) Sym Min Typ Max Units 0 - 400 kHz fSCL SCL clock frequency tLOW Clock low period 1.
Package mechanical data 6 M41T81S Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. SO8 – 8-lead plastic small package outline h x 45° A2 A c ccc b e 0.
M41T81S Package mechanical data Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline SOX18 Note: Drawing is not to scale. Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 2.57 2.44 2.69 0.101 0.096 0.106 A1 0.23 0.15 0.31 0.009 0.006 0.012 A2 2.34 2.29 2.39 0.092 0.090 0.094 B 0.46 0.41 0.51 0.018 0.016 0.020 c 0.25 0.20 0.31 0.
Part numbering 7 M41T81S Part numbering Table 16. Ordering information Example: M41T 81S M 6 F Device type M41T Supply voltage and write protect voltage 81S = VCC = 2.7 to 5.5 V Package M = SO8 MY(1) = SOX18 Temperature range 6 = –40 °C to 85 °C Shipping method E = ECOPACK® package, tubes(2) F = ECOPACK® package, tape & reel 1. The SOX18 package includes an embedded 32,768 Hz crystal. Contact local ST sales office for availability. 2. Shipment in tubes is not recommended for new design.
M41T81S 8 Revision history Revision history Date Revision Changes 22-Jan-2004 0.1 First draft 06-Feb-2004 0.2 Update BL information, characteristics, ratings, and Lead (Pb)-free information (Table 12, Table 6, Table 10, Table 16) 20-Feb-2004 0.3 Update characteristics (Table 11, Table 12, Table 7, Part numbering) 14-Apr-2004 1 05-May-2004 1.1 Update DC characteristics (Table 9) 16-Jun-2004 1.
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