Datasheet

M41T81 Operation
Doc ID 7529 Rev 10 9/29
Figure 4. Serial bus data transfer sequence
Figure 5. Acknowledgement sequence
2.2 READ mode
In this mode the master reads the M41T81 slave after setting the slave address (see
Figure 7 on page 10). Following the WRITE mode control bit (R/W
=0) and the acknowledge
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W
=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
Note: This is true both in READ mode and WRITE mode.
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB