Datasheet

Operation M41T66
8/34 Doc ID 15108 Rev 2
2 Operation
The M41T66 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 16 bytes
contained in the device can then be accessed sequentially in the following order:
● 1
st
byte: tenths/hundredths of a second register
● 2
nd
byte: seconds register
● 3
rd
byte: minutes register
● 4
th
byte: hours register
● 5
th
byte: square wave/day register
● 6
th
byte: date register
● 7
th
byte: century/month register
● 8
th
byte: year register
● 9
th
byte: calibration register
● 10
th
byte: watchdog register
● 11
th
- 15
th
bytes: alarm registers
● 16
th
byte: flags register
2.1 2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.