Datasheet

M41T66 Clock operation

Doc ID 15108 Rev 2 19/34

3.4 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the Watchdog

Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution

where:

000=1/16 second (16Hz)

001=1/4 second (4Hz)

010=1 second (1Hz)

011=4 seconds (1/4Hz) and

100 = 1 minute (1/60Hz)

Note: Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting the

BMB4-BMB0 = 0 with any combination of RB2-RB0, other than 000, will result in an

immediate watchdog time-out.

The amount of time-out is then determined to be the multiplication of the five-bit multiplier

value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3

seconds). If the processor does not reset the timer within the specified period, the M41T66

sets the WDF (watchdog flag) and generates an interrupt on the IRQ

/OUTpin. The

watchdog timer can only be reset by having the microprocessor perform a WRITE of the

watchdog register. The time-out period then starts over.

Should the watchdog timer time-out, any value may be written to the watchdog register in

order to clear the IRQ

/OUT pin. A value of 00h will disable the watchdog function until it is

again programmed to a new value. A READ of the flags register will reset the watchdog flag

(bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up, and

the watchdog register is cleared.

Note: A WRITE to any clock register will restart the watchdog timer.