Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. M41T62 logic diagram
- Figure 2. M41T63 logic diagram
- Figure 3. M41T64 logic diagram
- Figure 4. M41T65 logic diagram
- Figure 5. M41T62 connections
- Figure 6. M41T63 connections
- Figure 7. M41T64 connections
- Figure 8. M41T65 connections
- Table 2. Signal names
- Figure 9. M41T62 block diagram
- Figure 10. M41T63 block diagram
- Figure 11. M41T64 block diagram
- Figure 12. M41T65 block diagram
- Figure 13. Hardware hookup for SuperCap™ backup operation
- 2 Operation
- 3 Clock operation
- 3.1 RTC registers
- 3.2 Calibrating the clock
- 3.3 Setting alarm clock registers
- 3.4 Watchdog timer
- 3.5 Watchdog output (WDO - M41T63/65 only)
- 3.6 Square wave output (M41T62/63/64)
- 3.7 Full-time 32 KHz square wave output (M41T64)
- 3.8 Century bits
- 3.9 Leap year
- 3.10 Output driver pin (M41T62/65)
- 3.11 Oscillator stop detection
- 3.12 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- Table 12. Operating and AC measurement conditions
- Figure 25. AC measurement I/O waveform
- Figure 26. Crystal isolation example
- Table 13. Capacitance
- Table 14. DC characteristics
- Table 15. Crystal electrical characteristics
- Table 16. Crystals suitable for use with M41T6x series RTCs
- Table 17. Oscillator characteristics
- Figure 27. Bus timing requirements sequence
- Table 18. AC characteristics
- 6 Package mechanical information
- Figure 28. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline
- Table 19. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data
- Figure 29. QFN16 - 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint
- Figure 30. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, outline
- Table 20. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data
- Figure 31. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, recommended footprint
- Figure 32. Carrier tape for QFN16 3 mm x 3 mm package
- Table 21. Carrier tape dimensions for QFN16 3 mm x 3 mm package
- Figure 33. Carrier tape for LCC8 1.5 mm x 3.2 mm package
- Figure 34. Reel schematic
- Table 22. Reel dimensions for 12 mm carrier tape - QFN16 and LCC8 packages
- 7 Part numbering
- 8 Revision history
Operation M41T62, M41T63, M41T64, M41T65
12/44 DocID10397 Rev 20
2 Operation
The M41T6x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 16 bytes
contained in the device can then be accessed sequentially in the following order:
• 1
st
byte: tenths/hundredths of a second register
• 2
nd
byte: seconds register
• 3
rd
byte: minutes register
• 4
th
byte: hours register
• 5
th
byte: square wave/day register
• 6
th
byte: date register
• 7
th
byte: century/month register
• 8
th
byte: year register
• 9
th
byte: calibration register
• 10
th
byte: watchdog register
• 11
th
- 15
th
bytes: alarm registers
• 16th byte: flags register
2.1 2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high.
• Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.