M41T62, M41T63 M41T64, M41T65 Low-power serial real-time clocks (RTCs) with alarm Datasheet - production data • 32 KHz square wave output is on at power-up. Suitable for driving a microcontroller in lowpower mode. Can be disabled. (M41T62/63/64) 3mm 3mm • Programmable 1 Hz to 32 KHz square wave output (M41T62/63/64) QFN16, 3 mm x 3 mm • Programmable alarm with interrupt function (M41T62/65) 1.5 mm 3.
Table of contents M41T62, M41T63, M41T64, M41T65 Table of contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T62, M41T63, M41T64, M41T65 8 Table of contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of tables M41T62, M41T63, M41T64, M41T65 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. 4/44 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T62, M41T63, M41T64, M41T65 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 M41T62, M41T63, M41T64, M41T65 Description The M41T6x is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator. Eight registers are used for the clock/calendar function and are configured in binary-coded decimal (BCD) format. An additional eight registers provide status/control of alarm, 32 KHz output, calibration, and watchdog functions. Addresses and data are transferred serially via a two-line, bidirectional I2C interface.
M41T62, M41T63, M41T64, M41T65 Description Figure 2. M41T63 logic diagram VCC XI (1) XO WDO M41T63 SCL (2) SQW SDA VSS AI09189 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 3. M41T64 logic diagram VCC XI SQW(1) XO M41T64 SCL F32K(2) SDA VSS AI09108 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 4. M41T65 logic diagram VCC XI WDO(1) XO M41T65 SCL IRQ/FT/OUT(1) SDA VSS AI09109 1. Open drain.
Description M41T62, M41T63, M41T64, M41T65 VSS 3 (1) 4 SQW NC VCC NC 13 QFN 5 6 7 8 NC 2 14 NC XO 15 NC 1 16 VSS XI NC Figure 5. M41T62 connections 8 SCL 7 NC 3 6 IRQ/OUT(2) 4 5 VCC SDA 1 SQW(1) 2 SCL VSS SDA NC 12 NC 11 IRQ/OUT(2) 10 9 LCC AI09100 1. SQW output defaults to 32 KHz upon power-up. 2. Open drain. NC NC VCC NC Figure 6.
M41T62, M41T63, M41T64, M41T65 Description NC NC VCC NC Figure 8. M41T65 connections 16 15 14 13 XO 2 11 IRQ/FT/OUT VSS 3 10 SCL (1) 4 9 SDA WDO 5 6 7 8 NC NC NC 12 NC 1 VSS XI (1) AI09102 1. Open drain. Table 2.
Description M41T62, M41T63, M41T64, M41T65 Figure 10. M41T63 block diagram REAL TIME CLOCK CALENDAR XTAL OSCILLATOR FAIL DETECT 32KHz OSCILLATOR RTC W/ALARM SDA WATCHDOG I2C INTERFACE WDO SQWE SQUARE WAVE SCL (1) SQW(2) AI09191 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 11. M41T64 block diagram 32KE F32K(1) REAL TIME CLOCK CALENDAR XTAL OSCILLATOR FAIL DETECT 32KHz OSCILLATOR RTC W/ALARM SDA WATCHDOG I2C INTERFACE SQUARE WAVE SCL SQWE SQW(2) AI09192 1.
M41T62, M41T63, M41T64, M41T65 Description Figure 13. Hardware hookup for SuperCap™ backup operation VCC (1) MCU M41T6x VCC XI XO VSS VCC (2) IRQ/FT/OUT (3) WDO (4) SQW Port Reset Input SQWIN SCL Serial Clock Line SDA Serial Data Line F32K 32KHz CLKIN AI10400b 1. Diode required on open drain pin (M41T65 only) for SuperCap (or battery) backup. Low threshold BAT42 diode recommended. 2. For M41T62 and M41T65 (open drain). 3. For M41T63 and M41T65 (open drain). 4. For M41T64 (open drain).
Operation 2 M41T62, M41T63, M41T64, M41T65 Operation The M41T6x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be accessed sequentially in the following order: 2.
M41T62, M41T63, M41T64, M41T65 2.1.4 Operation Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition.
Operation M41T62, M41T63, M41T64, M41T65 Figure 15. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCL FROM MASTER 1 DATA OUTPUT BY TRANSMITTER 2 8 MSB 9 LSB DATA OUTPUT BY RECEIVER AI00601 2.2 READ mode In this mode the master reads the M41T6x slave after setting the slave address (see Figure 17 on page 15). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer.
M41T62, M41T63, M41T64, M41T65 Operation DATA n+1 SLAVE ADDRESS ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 17. READ mode sequence STOP SLAVE ADDRESS P NO ACK DATA n+X AI00899 STOP P NO ACK SLAVE ADDRESS DATA n+X ACK BUS ACTIVITY: DATA n+1 ACK DATA n ACK S ACK SDA LINE R/W BUS ACTIVITY: MASTER START Figure 18.
Operation 2.3 M41T62, M41T63, M41T64, M41T65 WRITE mode In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is shown in Figure 19 on page 16. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address “An” will follow and is to be written to the on-chip address pointer.
M41T62, M41T63, M41T64, M41T65 3 Clock operation Clock operation The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC.
Clock operation 3.1 M41T62, M41T63, M41T64, M41T65 RTC registers The M41T6x user interface is comprised of 16 memory mapped registers which include clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock counters are accessed indirectly via a set of buffer/transfer registers while the other eight registers are directly accessed. Data in the clock and alarm registers is in BCD format. Figure 20.
M41T62, M41T63, M41T64, M41T65 Clock operation Write timing When writing to the device, the data is shifted into the M41T62's I2C interface on the rising edge of the SCL signal. As shown in Figure 20, on the 8th clock cycle, the data is transferred from the I2C block into whichever register is being pointed to by the address pointer (not shown).
Clock operation M41T62, M41T63, M41T64, M41T65 Table 3. M41T62 register map Addr D7 00h D6 D5 D4 D3 0.1 seconds D2 D0 0.
M41T62, M41T63, M41T64, M41T65 Clock operation Table 4. M41T63 register map Addr D7 00h D6 D5 D4 D3 0.1 seconds D2 D1 D0 Function/range BCD format 0.
Clock operation M41T62, M41T63, M41T64, M41T65 Table 5. M41T64 register map Addr D7 00h D6 D5 D4 D3 0.1 seconds D2 D0 0.
M41T62, M41T63, M41T64, M41T65 Clock operation Table 6. M41T65 register map Addr D7 00h D6 D5 D4 D3 0.1 seconds D2 D1 D0 Function/range BCD format 0.
Clock operation 3.2 M41T62, M41T63, M41T64, M41T65 Calibrating the clock The M41T6x real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. This provides the time-base for the RTC. The accuracy of the clock depends on the frequency accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed.
M41T62, M41T63, M41T64, M41T65 Clock operation Figure 21. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 ΔF = K x (T – T )2 O F –80 2 2 K = –0.036 ppm/°C ± 0.006 ppm/°C –100 TO = 25°C ± 5°C –120 –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 Temperature °C 60 70 80 AI07888 Figure 22.
Clock operation 3.3 M41T62, M41T63, M41T64, M41T65 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Table 7 on page 26 shows the possible configurations.
M41T62, M41T63, M41T64, M41T65 3.4 Clock operation Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution where: 000=1/16 second (16 Hz); 001=1/4 second (4 Hz); 010=1 second (1 Hz); 011=4 seconds (1/4 Hz); and 100 = 1 minute (1/60 Hz).
Clock operation 3.6 M41T62, M41T63, M41T64, M41T65 Square wave output (M41T62/63/64) The M41T62/63/64 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency. These frequencies are listed in Table 8. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
M41T62, M41T63, M41T64, M41T65 3.8 Clock operation Century bits The two century bits, CB1 and CB0, are bits D7 and D6, respectively, in the century/month register at address 06h. Together, they comprise a 2-bit counter which increments at the turn of each century. CB1 is the most significant bit. The user may arbitrarily assign the meaning of CB1:CB0 to represent any century value, but the simplest way of using these bits is to extend the year register (07h) by mapping them directly to bits 9 and 8.
Clock operation 3.10 M41T62, M41T63, M41T64, M41T65 Output driver pin (M41T62/65) When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the calibration register. In other words, when D7 (OUT bit) is a '0,' then the IRQ/OUT pin will be driven low. Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor. 3.
M41T62, M41T63, M41T64, M41T65 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 11.
DC and AC parameters 5 M41T62, M41T63, M41T64, M41T65 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 12.
M41T62, M41T63, M41T64, M41T65 DC and AC parameters Table 13. Capacitance Parameter(1)(2) Symbol CIN COUT(3) tLP Min Max Unit Input capacitance - 7 pF Output capacitance - 10 pF Low-pass filter input time constant (SDA and SCL) - 50 ns 1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested. 2. At 25°C, f = 1 MHz. 3. Outputs deselected. Table 14.
DC and AC parameters M41T62, M41T63, M41T64, M41T65 Table 15. Crystal electrical characteristics Parameter(1)(2) Sym fO Resonant frequency Min Typ - 32.768 RS Series resistance (TA = –40 to 70 °C, oscillator startup at 2.0 V) - CL Load capacitance - Max Units kHz (3)(4) 75 6 kΩ pF 1. For the QFN16 package, user-supplied external crystals are required.
M41T62, M41T63, M41T64, M41T65 DC and AC parameters Table 17. Oscillator characteristics Symbol Parameter VSTA Oscillator start voltage tSTA Oscillator start time Cg XIN capacitance Cd XOUT capacitance Conditions Min ≤ 10 seconds 1.5 Typ Max V VCC = 3.0 V IC-to-IC frequency variation (1)(2) Unit 1 s 12 pF 12 pF –10 +10 ppm 1. Reference value. TA = 25 °C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by Citizen, CL = Cg • Cd / (Cg + Cd). 2.
Package mechanical information 6 M41T62, M41T63, M41T64, M41T65 Package mechanical information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
M41T62, M41T63, M41T64, M41T65 Package mechanical information Figure 28. QFN16 – 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline D E A3 A A1 ddd C e b L K 1 2 Ch E2 3 K D2 QFN16-A Note: Drawing is not to scale. Table 19. QFN16 – 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data Symb mm inches Typ Min Max Typ Min Max 0.90 0.80 1.00 0.035 0.032 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 – – 0.008 – – b 0.25 0.
Package mechanical information M41T62, M41T63, M41T64, M41T65 Figure 29. QFN16 – 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint 1.60 3.55 2.0 0.28 Note: AI09126 Dimensions shown are in millimeters (mm). Figure 30. LCC8 — 8-pin, 1.5 mm x 3.
M41T62, M41T63, M41T64, M41T65 Package mechanical information Table 20. LCC8 — 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data Symb mm inches Min Typ Max Min Typ Max b 0.30 0.40 0.50 0.012 0.016 0.020 D 1.40 1.50 1.60 0.055 0.059 0.063 D1 0.40 0.50 0.60 0.016 0.020 0.024 E 3.10 3.20 3.30 0.122 0.126 0.130 E1 2.20 2.30 2.40 0.087 0.091 0.094 A 0.80 e L 0.031 0.90 0.32 0.035 0.42 N 0.52 0.013 0.017 8 0.020 8 Figure 31. LCC8 — 8-pin, 1.
Package mechanical information M41T62, M41T63, M41T64, M41T65 Figure 32. Carrier tape for QFN16 3 mm x 3 mm package P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 21. Carrier tape dimensions for QFN16 3 mm x 3 mm package Package W D QFN16 12.00 ±0.30 1.50 +0.10 /-0.00 E P0 P2 F 1.75 4.00 2.00 5.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T Unit 3.30 ±0.10 3.30 ±0.10 1.10 ±0.10 8.00 ±0.10 0.30 ±0.05 1.75 ±0.
M41T62, M41T63, M41T64, M41T65 Package mechanical information Figure 34. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start 2.5mm min.width AM04928v1 Table 22. Reel dimensions for 12 mm carrier tape - QFN16 and LCC8 packages A B (max) (min) QFN16 330 mm (13-inch) 1.5 mm LCC8 180 mm (7-inch) 1.5 mm Package Note: D N (min) (min) 13 mm ± 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/–0 mm 13 mm ± 0.2 mm 20.
Part numbering 7 M41T62, M41T63, M41T64, M41T65 Part numbering Table 23. Ordering information scheme Example: M41T 62 Q 6 F Device family M41T Device type and supply voltage 62 = VCC = 1.3 V to 4.4 V 63(1) = VCC = 1.3 V to 4.4 V 64 = VCC = 1.3 V to 4.4 V 65 = VCC = 1.3 V to 4.4 V Package Q = QFN16 (3 mm x 3 mm) LC = LCC8 (1.5 mm x 3.2 mm) (M41T62 only) Temperature range 6 = –40 °C to 85 °C Shipping method F = ECOPACK® package, tape & reel 1. Contact the ST sales office for availability.
M41T62, M41T63, M41T64, M41T65 8 Revision history Revision history Table 24. Document revision history Date Revision 26-Jan-2010 12 Minor textual changes; updated Section 3.2; footnote 3 in Table 11; footnote 1 in Table 15; text in Section 6; Table 16, 18. 07-May-2010 13 Updated title of datasheet, Features, Section 1, Section 3.1, 3.2, 3.4, 3.11, Section 4, Figure 23, Table 16; added Figure 20, added embedded crystal package LCC8 (updated Figure 1, 5, 29, Table 23).
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