Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. M41T62 logic diagram
- Figure 2. M41T63 logic diagram
- Figure 3. M41T64 logic diagram
- Figure 4. M41T65 logic diagram
- Figure 5. M41T62 connections
- Figure 6. M41T63 connections
- Figure 7. M41T64 connections
- Figure 8. M41T65 connections
- Table 2. Signal names
- Figure 9. M41T62 block diagram
- Figure 10. M41T63 block diagram
- Figure 11. M41T64 block diagram
- Figure 12. M41T65 block diagram
- Figure 13. Hardware hookup for SuperCap™ backup operation
- 2 Operation
- 3 Clock operation
- 3.1 RTC registers
- 3.2 Calibrating the clock
- 3.3 Setting alarm clock registers
- 3.4 Watchdog timer
- 3.5 Watchdog output (WDO - M41T63/65 only)
- 3.6 Square wave output (M41T62/63/64)
- 3.7 Full-time 32 KHz square wave output (M41T64)
- 3.8 Century bits
- 3.9 Leap year
- 3.10 Output driver pin (M41T62/65)
- 3.11 Oscillator stop detection
- 3.12 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- Table 12. Operating and AC measurement conditions
- Figure 25. AC measurement I/O waveform
- Figure 26. Crystal isolation example
- Table 13. Capacitance
- Table 14. DC characteristics
- Table 15. Crystal electrical characteristics
- Table 16. Crystals suitable for use with M41T6x series RTCs
- Table 17. Oscillator characteristics
- Figure 27. Bus timing requirements sequence
- Table 18. AC characteristics
- 6 Package mechanical information
- Figure 28. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline
- Table 19. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data
- Figure 29. QFN16 - 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint
- Figure 30. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, outline
- Table 20. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data
- Figure 31. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, recommended footprint
- Figure 32. Carrier tape for QFN16 3 mm x 3 mm package
- Table 21. Carrier tape dimensions for QFN16 3 mm x 3 mm package
- Figure 33. Carrier tape for LCC8 1.5 mm x 3.2 mm package
- Figure 34. Reel schematic
- Table 22. Reel dimensions for 12 mm carrier tape - QFN16 and LCC8 packages
- 7 Part numbering
- 8 Revision history
Clock operation M41T62, M41T63, M41T64, M41T65
30/44 DocID10397 Rev 20
3.10 Output driver pin (M41T62/65)
When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the
IRQ
/OUT pin becomes an output driver that reflects the contents of D7 of the calibration
register. In other words, when D7 (OUT bit) is a '0,' then the IRQ
/OUT pin will be driven low.
Note: The IRQ
/OUT pin is an open drain which requires an external pull-up resistor.
3.11 Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator.
The following conditions can cause the OF bit to be set:
• The first time power is applied (defaults to a '1' on power-up).
Note: If the OF bit cannot be written to '0' four (4) seconds after the initial power-up, the STOP bit
(ST) should be written to a '1,' then immediately reset to '0.'
• The voltage present on V
CC
or battery is insufficient to support oscillation.
• The ST bit is set to '1.'
• External interference of the crystal
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ
pin will also be
activated. The IRQ
output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading
the flag register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run
for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event occurs
during a power-down condition, this bit will be set correctly.
3.12 Initial power-on defaults
Upon application of power to the device, the register bits will initially power-on in the state
indicated in Table 10.
Table 10. Initial power-on default values
Condition Device ST OF OFIE OUT FT AFE SQWE 32KE RS3-1 RS0 Watchdog
Initial
power-up
(1)
1. All other control bits power up in an undetermined state.
M41T62 0 1 0 1 N/A 0 1 N/A 0 1 0
M41T63 0 1 N/A N/A N/A N/A 1 N/A 0 1 0
M41T64 0 1 N/A N/A N/A N/A 0 1 0 1 0
M41T65 0 1 0 1 0 0 N/A N/A N/A N/A 0