Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Description
- Figure 1. M41T62 logic diagram
- Figure 2. M41T63 logic diagram
- Figure 3. M41T64 logic diagram
- Figure 4. M41T65 logic diagram
- Figure 5. M41T62 connections
- Figure 6. M41T63 connections
- Figure 7. M41T64 connections
- Figure 8. M41T65 connections
- Table 2. Signal names
- Figure 9. M41T62 block diagram
- Figure 10. M41T63 block diagram
- Figure 11. M41T64 block diagram
- Figure 12. M41T65 block diagram
- Figure 13. Hardware hookup for SuperCap™ backup operation
- 2 Operation
- 3 Clock operation
- 3.1 RTC registers
- 3.2 Calibrating the clock
- 3.3 Setting alarm clock registers
- 3.4 Watchdog timer
- 3.5 Watchdog output (WDO - M41T63/65 only)
- 3.6 Square wave output (M41T62/63/64)
- 3.7 Full-time 32 KHz square wave output (M41T64)
- 3.8 Century bits
- 3.9 Leap year
- 3.10 Output driver pin (M41T62/65)
- 3.11 Oscillator stop detection
- 3.12 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- Table 12. Operating and AC measurement conditions
- Figure 25. AC measurement I/O waveform
- Figure 26. Crystal isolation example
- Table 13. Capacitance
- Table 14. DC characteristics
- Table 15. Crystal electrical characteristics
- Table 16. Crystals suitable for use with M41T6x series RTCs
- Table 17. Oscillator characteristics
- Figure 27. Bus timing requirements sequence
- Table 18. AC characteristics
- 6 Package mechanical information
- Figure 28. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline
- Table 19. QFN16 - 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data
- Figure 29. QFN16 - 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint
- Figure 30. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, outline
- Table 20. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data
- Figure 31. LCC8 - 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, recommended footprint
- Figure 32. Carrier tape for QFN16 3 mm x 3 mm package
- Table 21. Carrier tape dimensions for QFN16 3 mm x 3 mm package
- Figure 33. Carrier tape for LCC8 1.5 mm x 3.2 mm package
- Figure 34. Reel schematic
- Table 22. Reel dimensions for 12 mm carrier tape - QFN16 and LCC8 packages
- 7 Part numbering
- 8 Revision history

DocID10397 Rev 20 17/44
M41T62, M41T63, M41T64, M41T65 Clock operation
3 Clock operation
The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The eight byte clock register (see Table 3: M41T62 register map, Table 4: M41T63 register
map, Table 5: M41T64 register map, and Table 6: M41T65 register map) is used to both set
the clock and to read the date and time from the clock, in a binary-coded decimal format.
Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to
“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and
07h contain the date (day of month), month, and years. The ninth clock register is the
calibration register (this is described in the clock calibration section). Bit D7 of register 01h
contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When
reset to a '0' the oscillator restarts within one second (typical).
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bit D7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (OFIE).
When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see
Oscillator stop detection on page 30) will also generate an interrupt output.
Bits D6 and D7 of clock register 06h (century/month register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1).
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the OFIE bit, RS0-RS3 bit, and CB0-CB1 bits will result in an update of the system
clock and a reset of the divider chain. This could result in an inadvertent change of the
current time. These non-clock related bits should be written prior to setting the clock, and
remain unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.