Datasheet

Operation M41T62, M41T63, M41T64, M41T65
16/44 DocID10397 Rev 20
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is
shown in Figure 19 on page 16. Following the START condition and slave address, a logic
'0' (R/W
=0) is placed on the bus and indicates to the addressed device that word address
“An” will follow and is to be written to the on-chip address pointer. The data word to be
written to the memory is strobed in next and the internal address pointer is incremented to
the next address location on the reception of an acknowledge clock. The M41T6x slave
receiver will send an acknowledge clock to the master transmitter after it has received the
slave address see Figure 16 on page 14 and again after it has received the word address
and each data byte.
Figure 19. WRITE mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK ACK ACK ACK
STOP START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS