Datasheet

Operation M41T60
12/28 DocID10396 Rev 14
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic
'0' (R/W
= 0) is placed on the bus and indicates to the addressed device that word address
An will follow and is to be written to the on-chip address pointer. The data word to be written
to the memory is strobed in next and the internal address pointer is increased to the next
address location on the reception of an acknowledge clock. The M41T60 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and each data byte.
Figure 10. WRITE mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK ACK ACK ACK
STOP START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+ 1 DATA n+ X
WORD
ADDRESS (An)
SLAVE
ADDRESS