M41T60 Low-power serial real-time clock (RTC) Datasheet - production data Features • Counters for seconds, minutes, hours, day, date, month, years, and century • 32 KHz crystal oscillator integrating load capacitance and high crystal series resistance operation QFN16 3 mm x 3 mm • Oscillator stop detection monitors clock operation • Serial interface supports I2C bus (400 kHz) VSOJ20 (47.6mm2) • 350 nA timekeeping current at 3 V 2 GND Plane Guard Ring (21.
Table of contents M41T60 Table of contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 3 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.
M41T60 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Examples using century bits . . . . . . . . . . . . . . . . . . . . . .
List of figures M41T60 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. 4/28 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 16-pin QFN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T60 1 Description Description The M41T60 is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator (external crystal controlled). Eight registers are used for the clock/calendar function and are configured in binary-coded decimal (BCD) format. Addresses and data are transferred serially via a two-line, bidirectional bus. The built-in address register is increased automatically after each WRITE or READ data byte.
Description M41T60 NC NC VCC NC Figure 2. 16-pin QFN connections 16 15 14 13 XO 2 11 OFIRQ/OUT(1) VSS 3 10 SCL (1) 4 9 SDA FT 5 6 7 8 NC NC NC 12 NC 1 VSS XI AI08870 Figure 3. Block diagram (1) FT FT OUT OFIE 1 Hz (1) OFIRQ/OUT OSCILLATOR FAIL DETECT XI OSCILLATOR 32.768 kHz DIVIDER SECONDS XO MINUTES HOURS CONTROL LOGIC VCC VSS DAY DATE SCL CENTURY/ MONTH SERIAL BUS INTERFACE SDA YEAR ADDRESS REGISTER CALIBRATION AI08871 1. Open drain output.
M41T60 Description Figure 4. Hardware hookup for SuperCap™ backup operation VCC MCU M41T60 VCC XI XO VSS VCC (1) OFIRQ/OUT (1) FT Port Port SCL Serial Clock Line SDA Serial Data Line AI10476b 1. Open drain output.
Operation 2 M41T60 Operation The M41T60 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 2.1 1. Seconds register 2. Minutes register 3. Hours register 4. Day register 5. Date register 6. Century/month register 7. Years register 8.
M41T60 2.1.4 Operation Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited.
Operation M41T60 Figure 6. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCL FROM MASTER 1 DATA OUTPUT BY TRANSMITTER 2 8 MSB 9 LSB DATA OUTPUT BY RECEIVER AI00601 2.2 READ mode In this mode, the master reads the M41T60 slave after setting the slave address (see Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address An is written to the on-chip address pointer.
M41T60 Operation DATA n+1 ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 8. READ mode sequence SLAVE ADDRESS STOP SLAVE ADDRESS P NO ACK DATA n+X AI00899 STOP SLAVE ADDRESS DATA n+X ACK BUS ACTIVITY: DATA n+1 ACK DATA n P NO ACK R/W S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 9.
Operation 2.3 M41T60 WRITE mode In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer.
M41T60 3 Clock operation Clock operation The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The eight-byte clock register (see Table 2 on page 15) is used to both set the clock and to read the date and time from the clock, in a binary-coded decimal format. Seconds, minutes, and hours are contained within the first three registers.
Clock operation M41T60 These bits can be set to represent any value between 0 and 31 in binary format. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles.
M41T60 Clock operation Table 2. Register map Data Function/range BCD format Address D7 D6 D5 D4 D3 D2 D1 D0 0 ST 10 seconds Seconds Seconds 00-59 1 OFIE 10 minutes Minutes Minutes 00-59 2 0 0 Hours Hours 00-23 3 0 0 Day 01-07 4 0 0 Date 01-31 5 CB1 CB0 6 10 hours 0 0 0 Day 10 date 0 Date 10 M.
Clock operation M41T60 Figure 12. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594b 3.2 Century bits The two century bits, CB1 and CB0, are bits D7 and D6, respectively, in the century/month register at address 06h. Together, they comprise a 2-bit counter which increments at the turn of each century. CB1 is the most significant bit.
M41T60 3.3 Clock operation Leap year Leap year occurs every four years, in years which are multiples of 4. For example, 2012 was a leap year. An exception to that is any year which is a multiple of 100. For example, the year 2100 is not a leap year. A further exception is that years which are multiples of 400 are indeed leap years. Hence, while 2100 is not a leap year, 2400 is. During any year which is a multiple of 4, the M41T6x RTC will automatically insert leap day, February 29.
Maximum ratings 4 M41T60 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4.
M41T60 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5.
DC and AC parameters M41T60 Table 6. Capacitance Parameter (1)(2) Symbol CIN COUT(3) tLP Min Max Unit Input capacitance (SCL) - 7 pF Output capacitance (SDA, OUT) - 10 pF Low-pass filter input time constant (SDA and SCL) - 50 ns 1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. Table 7.
M41T60 DC and AC parameters Table 8. Crystal electrical characteristics Parameter (1)(2) Symbol Min Typ 32.768 fO Resonant frequency - RS Series resistance (TA = –40 to 70°C, oscillator startup at 2.0 V) - CL Load capacitance - Max Unit kHz 75 (3)(4) kΩ 6 pF 1. For the QFN16 package, user-supplied, external crystals are required. The 6 and 7 pF crystals listed in Table 9 below have been evaluated by ST and have been found to be satisfactory for use with the M41T6x series RTCs. 2.
DC and AC parameters M41T60 Table 10. Oscillator characteristics Symbol Parameter VSTA Oscillator start voltage tSTA Oscillator start time Cg XIN capacitance Cd XOUT capacitance Conditions Min ≤ 10 seconds 1.5 Typ Max V VCC = 3.0 V IC-to-IC frequency variation (1) Unit 1 s 12 pF 12 pF –10 +10 ppm 1. Reference value. TA = 25 °C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by Citizen, CL = Cg • Cd / (Cg + Cd) Figure 16.
M41T60 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Package mechanical data M41T60 Figure 17. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline D E A3 A A1 ddd C e b L K 1 2 Ch E2 3 K D2 Note: QFN16-A Drawing is not to scale. Table 12. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data mm inches Dim Typ Min Max Typ Min Max A 0.90 0.80 1.00 0.035 0.032 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 – – 0.008 – – b 0.25 0.18 0.30 0.010 0.007 0.
M41T60 Package mechanical data Figure 18. QFN16, quad, flat package, no lead, 3 x 3 mm, recommended footprint 1.60 3.55 2.0 0.28 Note: AI09126 Substrate pad should be tied to VSS. Figure 19. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data 7.0 ± 0.3 VSOJ20 6.0 ± 0.2 3.2 SMT CRYSTAL 1 XI 2 XO 2.9 3 4 1.5 ST QFN16 2.9 AI11146 Note: Dimensions shown are in millimeters (mm).
Part numbering 7 M41T60 Part numbering Table 13. Ordering information scheme Example: M41T 60 Q 6 F Device family M41T Device type and supply voltage 60 = VCC = 1.3 to 4.4 V Package Q = QFN16 (3 mm x 3 mm) Temperature range 6 = –40 to 85 °C Shipping method F = ECOPACK® package, tape & reel For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
M41T60 8 Revision history Revision history Table 14. Revision history Date Revision 13-Nov-2003 1 20-Nov-2003 1.1 25-Dec-2003 2 13-Jan-2004 2.1 Update characteristics (Figure 9, 10, 12; Table 7, 13) 26-Feb-2004 2.2 Update characteristics and mechanical dimensions (Figure 15, 18; Table 4 , 7, 12) 02-Mar-2004 2.
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