Datasheet

Operation M41T56
12/27 Doc ID 6104 Rev 9
2.3 Write mode
In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'
(R/W
= 0) is placed on the bus and indicates to the addressed device that word address A
n
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 7 on page 11).
2.4 Data retention mode
With valid V
CC
applied, the M41T56 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,
write protecting itself when V
CC
falls between V
PFD
(max) and V
PFD
(min). This is
accomplished by internally inhibiting access to the clock registers and SRAM. When V
CC
falls below the battery backup switchover voltage (V
SO
), power input is switched from the
V
CC
pin to the battery and the clock registers and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up, when V
CC
returns to a nominal value,
write protection continues for t
REC
.
For a further more detailed review of battery lifetime calculations, please see application
note AN1012.
Figure 10. Write mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK ACK ACK ACK
STOP START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS