M41T56 Serial real-time clock (RTC) with 56 bytes NVRAM Features ■ Counters for seconds, minutes, hours, day, date, month, years, and century ■ 32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation ■ Serial interface supports I2C bus (100 kHz protocol) ■ Ultra-low battery supply current of 450 nA (typ at 3 V) ■ 5 V ±10% supply voltage ■ Timekeeping down to 2.
Contents M41T56 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 3 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.
M41T56 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures M41T56 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 4/27 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41T56 1 Description Description The M41T56 is a low-power, serial real-time clock (RTC) with 56 bytes of NVRAM. A built-in 32,768 Hz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line, bidirectional bus. The built-in address register is incremented automatically after each WRITE or READ data byte.
Description M41T56 Table 1. Signal names OSCI Oscillator input OCSO Oscillator output FT/OUT Frequency test / output driver (open drain) SDA Serial data address input / output SCL Serial clock VBAT Battery supply voltage VCC Supply voltage VSS Ground Figure 2. 8-pin SOIC connections OSCI OSCO VBAT VSS M41T56 8 1 2 7 3 6 4 5 VCC FT/OUT SCL SDA AI02306B Figure 3. M41T56 block diagram 1 Hz OSCI OSCILLATOR 32.
M41T56 2 Operation Operation The M41T56 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds register 2. Minutes register 3. Century/hours register 4. Day register 5. Date register 6. Month register 7. Years register 8. Control register 9.
Operation 2.1.3 M41T56 Stop data transfer A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition. 2.1.4 Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.
M41T56 Operation Figure 5. Acknowledge sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCLK FROM MASTER 1 DATA OUTPUT BY TRANSMITTER 2 MSB 8 9 LSB DATA OUTPUT BY RECEIVER AI00601 Figure 6.
Operation M41T56 Table 2. AC characteristics Parameter(1) Symbol Min Max Unit 0 100 kHz fSCL SCL clock frequency tLOW Clock low period 4.7 µs tHIGH Clock high period 4 µs tR SDA and SCL rise time 1 µs tF SDA and SCL fall time 300 ns tHD:STA START condition hold time (after this period the first clock pulse is generated) tSU:STA tSU:DAT tHD:DAT (2) tSU:STO tBUF 4 µs START condition setup time (only relevant for a repeated start condition) 4.
M41T56 Operation Figure 7. Slave address location R/W START A LSB MSB SLAVE ADDRESS 1 1 0 1 0 0 0 AI00602 R/W SLAVE ADDRESS DATA n+1 ACK DATA n ACK ACK BUS ACTIVITY: S ACK WORD ADDRESS (n) S ACK SDA LINE R/W BUS ACTIVITY: MASTER START Read mode sequence START Figure 8.
Operation 2.3 M41T56 Write mode In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer.
M41T56 3 Clock operation Clock operation The eight byte clock register (see Table 3) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register) contain the century enable bit (CEB) and the century bit (CB).
Clock operation 3.1 M41T56 Clock calibration The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M41T56 improves to better than ±2 ppm at 25 °C. The oscillation rate of any crystal changes with temperature (see Figure 11 on page 15).
M41T56 Clock operation Figure 11. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 –80 ΔF = K x (T –T )2 O F –100 K = –0.036 ppm/°C2 ± 0.006 ppm/°C2 –120 TO = 25°C ± 5°C –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 Temperature °C AI00999b Figure 12. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 3.
Maximum ratings 4 M41T56 Maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4.
M41T56 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristics tables are derived from tests performed under the measurement conditions listed in Table 5: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
DC and AC parameters Table 7. Symbol M41T56 DC characteristics Test condition(1) Parameter Min Typ Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Switch frequency = 100 kHz 300 µA ILI Input leakage current ILO Output leakage current ICC1 Supply current ICC2 Supply current (standby) VIL Input low voltage –0.3 1.5 V VIH Input high voltage 3 VCC + 0.8 V VOL Output low voltage 0.4 V 3 3.
M41T56 DC and AC parameters Table 9. Power down/up mode AC characteristics Parameter(1) Symbol tPD SCL and SDA at VIH before power-down tFB Min Max Unit 0 ns VPFD (min) to VSS VCC fall time 300 µs tRB VSS to VPFD (min) VCC rise time 100 µs tREC SCL and SDA at VIH after power-up 10 µs 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V (except where noted). Table 10.
Package mechanical data 6 M41T56 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
M41T56 Package mechanical data Figure 15. SO8 – 8-pin plastic small package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A 1. Drawing is not to scale. Table 11. SO8 – 8-pin plastic small outline, package mechanical data millimetres inches Symbol Typ Min A Max Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.
Package mechanical data M41T56 Figure 16. Carrier tape for SO8 package (150-mil body width) P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 12. Carrier tape dimensions for SO8 package (150-mil body width) Package W D SO8 12.00 ±0.30 1.50 +0.10/ –0.00 22/27 E P0 P2 F 1.75 4.00 2.00 5.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 6.50 ±0.10 5.30 ±0.10 2.20 ±0.10 8.00 ±0.10 0.30 ±0.
M41T56 Package mechanical data Figure 17. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius Tape start 2.5mm min.width At hub AM04928v1 Table 13. Reel dimensions for 12 mm carrier tape - SO8 package (150-mil body width) A B (max) (min) 330 mm (13-inch) 1.5 mm Note: C 13 mm ± 0.2 mm D N (min) (min) 20.2 mm 60 mm G 12.4 mm + 2/–0 mm T (max) 18.
Part numbering 7 M41T56 Part numbering Table 14. Ordering information scheme Example: M41T 56 M Device type M41T Supply voltage and write protect voltage 56 = VCC = 4.5 to 5.5 V Package M = SO8 Temperature range 6 = –40 °C to 85 °C Shipping method E = Lead-free package (ECOPACK®), tubes(1) F = Lead-free package (ECOPACK®), tape & reel 1. Not recommended for new design. Contact local ST sales office for availability.
M41T56 8 References References ● The crystal component supplier KDS as cited in Table 8: Crystal electrical characteristics on page 18 can be contacted at http://www.kds.info/index_en.
Revision history M41T56 9 Revision history Table 15. Document revision history Date Revision Changes Mar-1999 1.0 First issue 23-Dec-1999 1.1 SOH28 package added 21-Mar-2000 1.2 Series resistance max value changed (Table 8) 30-Nov-2000 1.3 Added PSDIP8 package 25-Jan-2001 1.4 Corrected graphic, measurements of PSDIP8 (Figure 18, Table 14) 16-Feb-2001 2.0 Reformatted, table added (Table 16). 06-Apr-2001 2.1 Add temp.
M41T56 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.
