Datasheet

M41ST87Y, M41ST87W Clock operation
Doc ID 9497 Rev 10 35/54
Figure 25. Backup mode alarm waveform
3.4 Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and
11=4 seconds. The amount of time-out is then determined to be the multiplication of the five-
bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog
register = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M41ST87Y/W sets
the WDF (watchdog flag) and generates either a watchdog interrupt or a microprocessor
reset.
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0,' the watchdog will activate the IRQ
/OUT pin when timed-out. When WDS is set to
a '1,' the watchdog will output a negative pulse on the RST
pin for t
rec
. The watchdog
register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high)
can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a
WRITE of the watchdog register. The time-out period then starts over.
Note: The WDI pin should be tied to V
SS
if not used and is only available in the SOX28 package.
In order to perform a software reset of the watchdog timer, the original time-out period can
be written into the watchdog register, effectively restarting the count-down cycle.
AI07087
V
CC
IRQ/OUT
V
PFD
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
HIGH-Z
V
SO
HIGH-Z
t
rec