Datasheet

M41ST87Y, M41ST87W Clock operation
Doc ID 9497 Rev 10 31/54
3.2 Calibrating the clock
The M41ST87Y/W is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested to not exceed ±35 ppm (parts per million) oscillator
frequency error at 25
°
C, with ±20 ppm crystals, which translates to about ±1.53 minutes per
month. Even better accuracy can be achieved with higher accuracy crystals. When the
calibration circuit is properly employed, accuracy can be improved to better than ±2 ppm at
25 °C.
The oscillation rate of crystals changes with temperature (see Figure 22 on page 33).
Therefore, the M41ST87Y/W design employs periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,
as shown in Figure 23: Calibration waveform on page 33. The number of times pulses which
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Keys:
0 = Must be set to zero RB0-RB1 = Watchdog resolution bits
32kE = 32 kHz output enable bit RPT1-RPT5 = Alarm repeat mode bits
ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency
AF = Alarm flag (read only) S = Sign bit
AFE = Alarm flag enable bit SQWE = Square wave enable
BL = Battery low flag (read only) SQWOD = Square wave open drain bit
BMB0-BMB4 = Watchdog multiplier bits ST = Stop bit
CB0-CB1 = Century bits TB (1 and 2) = Tamper bits (read only)
CLR (1 and 2) = RAM clear bits TCHI/TCLO
(1 and 2) = Tamper current hi/tamper current low bits
CLR (1 and 2)
EXT
= RAM clear external bits TCM (1 and 2) = Tamper connect mode bits
CLRPW0 = RAM clear pulse width 0 bit TDS (1 and 2) = Tamper detect sampling bits
CLRPW1 = RAM clear pulse width 1 bit TEB (1 and 2) = Tamper enable bits
FT = Frequency test bit THS = Threshold bit
HT = Halt update bit TIE (1 and 2) = Tamper interrupt enable bits
OF = Oscillator fail bit TPM (1 and 2) = Tamper polarity mode bits
OFIE = Oscillator fail interrupt enable bit TR = t
rec
bit
OUT = Output level WDS = Watchdog steering bit
PFOD = Power-fail output open drain bit WDF = Watchdog flag (read only)