Datasheet

Operating modes M41ST87Y, M41ST87W
28/54 Doc ID 9497 Rev 10
2.11 Tamper event time-stamp
Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but
the event will also be automatically time-stamped. This is accomplished by freezing the
normal update of the clock registers (00h through 07h) immediately following a tamper
event. Thus, when tampering occurs, the user may first read the time registers to determine
exactly when the tamper event occurred, then re-enable the clock update to the current time
(and reset the tamper bit, TB
X
) by resetting the tamper enable bit (TEB
X
).
The time update will then resume and the clock can be read to determine the current time.
Both tamper enable bits (TEB
X
) must always be set to '0' in order to read the current time.
In the event of multiple tampers, the time-stamp will reflect the initial tamper event.
Note: If the TEB
X
bit is set, the tamper event time-stamp will take precedence over the power
down time-stamp (see Section 3.0.1: Power-down time-stamp on page 29) and the HT bit
(halt update) will not be set during the power-down event. If both are needed, the power
down time-stamp may be accomplished by writing the time into the general purpose RAM
memory space when PFO
is asserted.