Datasheet

M41ST87Y, M41ST87W Operating modes
Doc ID 9497 Rev 10 25/54
Table 5. Tamper detect timing
Figure 20. RAM clear hardware hookup (SOX28 package only)
1. Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an n-
channel enhancement mode MOSFET should be used to isolate the OUT pin from the V
OUT
of the M41ST87.
2. In order to avoid turning on an on-chip parasitic diode when driving V
OUT
negative, a p-channel enhancement mode
MOSFET should be used to isolate the V
OUT
pin from the negative voltage generated by the inverting charge pump.
Symbol Parameter
CLRPW
1
CLRPW
0
Min Typ Max Unit
t
CLRD
(1)
1. With input capacitance = 70 pF and resistance = 50 Ω.
Tamper RAM clear ext delay X X 1.0
(2)
2. If the OF bit is set, t
CLRD
(min) = 0.5 ms.
1.5 2.0 ms
t
CLR
Tamper clear timing
00 1 s
01 4 s
10 8 s
11 16 s
AI07804
V
CC
PFO
1
EX
SCL
M41ST87Y/W
WDI
RSTIN1
RSTIN2
PFI
1
PFI
2
V
SS
V
BAT
F
32k
IRQ/OUT
SQW/FT
RST
V
OUT
E
CON
SDA
CAP+ CAP–
Inverting
Charge
Pump
SHDN
OUTIN
TP1
IN
TP
CLR
TP2
IN
Pushbutton
Reset
PFO
2
Low-Power
SRAM
V
CC
Negative Output
(–1 x V
IN
)
E
To RST
To LED Display
(2)
(1)
To NMI
To INT
To 32kHz
Inhibit
5V
Regulator
V
CC
V
IN