Datasheet

M41ST87Y, M41ST87W Operating modes
Doc ID 9497 Rev 10 23/54
negative voltage generated by the charge pump during a tamper condition, and from being
pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN
=
logic low). The gates of both MOSFETs should be connected to TP
CLR
as shown in
Figure 20 on page 25. One n-channel enhancement MOSFET should be placed between
the output of the inverting charge pump and the V
OUT
of the M41ST87. The other MOSFET
should be an enhancement mode p-channel, and placed between V
OUT
of the M41ST87
and V
CC
of the external SRAM. When TP
CLR
goes high after a tamper condition occurs, the
n-channel MOSFET will turn on and the p-channel will turn off. During normal operating
conditions, TP
CLR
will be low and the p-channel will be on, while the n-channel will be off.
Table 4. Tamper detection current (normally closed - TCM
X
= '0')
Figure 17. Tamper detect sampling options
TDS
X
TCHI/TCLO
X
Tamper circuit mode Current at 3.0 V (typ)
(1)(2)
1. When calculating battery lifetime, this current should be added to I
BAT
current listed in Table 17 on page 44.
2. Per tamper detect input
Unit
0 0 Continuous monitoring / 10 MΩ pull-up/-down 0.3 µA
0 1 Continuous monitoring / 1 MΩ pull-up/-down 3.0 µA
1 0 Sampling (1 Hz) / 10 MΩ pull-up/-down 0.3 nA
1 1 Sampling (1 Hz) / 1 MΩ pull-up/-down 3.0 nA
AI07819
TAMPER LO,
NORMALLY OPEN
TAMPER HI,
NORMALLY CLOSED
User
Configuration
TDS
X
= 0
TDS
X
= 1
TDS
X
= 0
TDS
X
= 1
TAMPER HI,
NORMALLY OPEN
TAMPER LO,
NORMALLY CLOSED
CONTINUOUS
MONITORING
CONTINUOUS
MONITORING
CONTINUOUS
MONITORING
SAMPLED
MONITORING
CONTINUOUS
MONITORING
SAMPLED
MONITORING
V
CC
(V
OUT
)
V
CC
(V
OUT
)
V
CC
(V
OUT
)
TCM
X
, TPM
X