Datasheet

Operating modes M41ST87Y, M41ST87W
20/54 Doc ID 9497 Rev 10
Figure 14. Tamper detect connection options
Note: These options are summarized in Ta bl e 3 .
1. If the CLRX
EXT
bit is set, a second tamper to V
OUT
(TPM2 = '1') during t
CLR
will not be detected.
2. If the CLRX
EXT
bit is set, a second tamper to V
OUT
(TPM2 = '1') will trigger automatically.
3. Optional external resistor to V
CC
allows the user to bypass sampling when power is “on.”
Table 3. Tamper detection truth table
Option Mode TCM
X
TPM
X
I Normally open/tamper to GND
(1)
1. No battery current drawn during battery backup.
10
II Normally open/tamper to V
OUT
(1)
11
III Normally closed/tamper to GND 0 0
IV Normally closed/tamper to V
OUT
01
AI07075
TP
IN
TAMPER HI
(TPM
X
= 1)
TAMPER LO
(TPM
X
= 0)
V
OUT
(1)
TP
IN
NORMALLY
CLOSED
(TCM
X
= 0)
NORMALLY
OPEN
(TCM
X
= 1)
I.
IV.
II.
III.
TP
IN
V
OUT
(2)
TCHI/TCLO = 0
TCHI/TCLO = 1
TCHI/TCLO = 0TCHI/TCLO = 1
V
OUT
(Int)
V
CC
(3)