Datasheet

M41ST87Y, M41ST87W Operating modes
Doc ID 9497 Rev 10 19/54
2.6.2 Tamper bits (TB1 and TB2)
If the TEB
X
bit is set, and a tamper condition occurs, the TB
X
bit will be set to '1.' This bit is
“Read-only” and is reset only by setting the TEB
X
bit to '0.' These bits are located in the flags
register 0Fh.
2.6.3 Tamper interrupt enable bits (TIE1 and TIE2)
If this bit is set to a logic '1,' the IRQ/OUT pin will be activated when a tamper event occurs.
This function is also valid in battery backup if the ABE bit (alarm in battery backup) is also
set to '1' (see Figure 15 on page 21).
Note: In order to avoid an inadvertent activation of the IRQ
/OUT pin due to a prior tamper event,
the flag register (0Fh) should be read prior to clearing and again setting the TEB
X
bit.
2.6.4 Tamper connect mode bit (TCM1 and TCM2)
This bit indicates whether the position of the external switch selected by the user is in the
normally open (TCM
X
= '1') or normally closed (TCM
X
= '0') position (see Figure 14 on
page 20 and Figure 16 on page 21).
2.6.5 Tamper polarity mode bits (TPM1 and TPM2)
The state of this bit indicates whether the tamper pin input will be taken high (to V
OUT
if
TPM
X
= '1') or low (to V
SS
if TPM
X
= '0') to trigger a tamper event (see Figure 14 on page 20
and Figure 16 on page 21).