Datasheet

Operating modes M41ST87Y, M41ST87W
12/54 Doc ID 9497 Rev 10
2 Operating modes
The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 160 bytes
contained in the device can then be accessed sequentially in the following order:
00h. Tenths/hundredths of a second register
01h. Seconds register
02h. Minutes register
03h. Century/hours register
04h. Day register
05h. Date register
06h. Month register
07h. Year register
08h. Control register
09h. Watchdog register
0Ah-0Eh. Alarm registers
0Fh. Flag register
10h-12h. Reserved
13h. Square wave
14h. Tamper register 1
15h. Tamper register 2
16h-1Dh. Serial number (8 bytes)
1Eh-1Fh. Reserved (2 bytes)
20h-9Fh. User RAM (128 bytes)
The M41ST87Y/W clock continually monitors V
CC
for an out-of-tolerance condition. Should
V
CC
fall below V
PFD
, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent erroneous
data from being written to the device from a an out-of-tolerance system. When V
CC
falls
below V
SO
, the device automatically switches over to the battery and powers down into an
ultra low current mode of operation to conserve battery life. As system power returns and
V
CC
rises above V
SO
, the battery is disconnected, and the device is switched to external
V
CC
.
Write protection continues until t
rec
(min) elapses after V
CC
reaches V
PFD
(min).
For more information on battery storage life refer to application note AN1012.