M41ST87Y M41ST87W 5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM Features Embedded crystal ■ 5.0, 3.3, or 3.0 V operation ■ 400 kHz I2C bus ■ NVRAM supervisor to non-volatize external LPSRAM ■ 2.5 to 5.5 V oscillator operating voltage ■ Automatic switchover and deselect circuitry ■ Choice of power-fail deselect voltages – M41ST87Y: (not recommended for new design, contact ST sales office for availability) THS = 1: VPFD≈ 4.
Contents M41ST87Y, M41ST87W Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Bus not busy . .
M41ST87Y, M41ST87W Contents 3.1 TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 Square wave output . . . . . . . . . . .
List of tables M41ST87Y, M41ST87W List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. 4/54 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41ST87Y, M41ST87W List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 M41ST87Y, M41ST87W Description The M41ST87Y/W secure serial RTC and NVRAM supervisor is a low power 1280-bit, static CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator (internal crystal-controlled) and 8 bytes of the SRAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 11 bytes of RAM provide calibration, status/control of alarm, watchdog, tamper, and square wave functions.
M41ST87Y, M41ST87W Figure 1. Description Logic diagram VCC VBAT (4) XI VOUT (4) XO IRQ/OUT(1) SCL SQW/FT(2) SDA EX (3) ECON (3) RSTIN1 (3) RSTIN2 (3) WDI RST(1) M41ST87Y M41ST87W F32k(1) PFI1 PFO1(2) PFI2 PFO2(2) TP1IN (3) TPCLR TP2IN VSS AI07023 1. Open drain output. 2. Programmable output (open drain or full-CMOS). Defaults to open drain on first power-up. 3. Available in SOX28 package only. 4. Available in SSOP package only.
Description M41ST87Y, M41ST87W Figure 2. 28-pin, 300 mil SOIC connections NF NF NF NF NC NC PFO2 SQW/FT WDI RSTIN1 RSTIN2 PFO1 PFI2 VSS 1 28 2 27 26 3 25 4 24 5 23 6 7 22 M41ST87Y 8 M41ST87W 21 20 9 19 10 18 11 17 12 16 13 15 14 VCC EX IRQ/OUT VOUT TP2IN PFI1 SCL F32k TP1IN RST TPCLR SDA ECON VBAT AI07025b Note: No function (NF) and no connect (NC) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally shorted together. Figure 3.
M41ST87Y, M41ST87W Table 1.
Description Figure 4. M41ST87Y, M41ST87W Block diagram REAL TIME CLOCK CALENDAR 128 BYTES USER RAM SDA I2 C INTERFACE 8 BYTES ROM OFIE RTC w/ALARM & CALIBRATION SCL (4) Crystal XI VOUT WDS SQUARE WAVE XO 2 TPXIN WATCHDOG 32KHz OSCILLATOR AFE TIEX CLRX (3) TAMPER WDI VCC IRQ/OUT CLRXEXT (1) SQW/FT (2) TPCLR(3) VOUT VBAT F32k(1) VSS VBL COMPARE VSO COMPARE VPFD COMPARE BL POR RST RSTIN1 (1) (3) RSTIN2 (3) (3) ECON EX PFI1 COMPARE PFO1(2) COMPARE PFO2(2) 1.
M41ST87Y, M41ST87W Figure 5. Description Hardware hookup M41ST87Y/W Unregulated Voltage VIN VCC 5V Regulator (1) VCC TPCLR VOUT TP1IN ECON TP2IN EX VIN VCC 3.3V Regulator VCC (1) E (1) Low-Power SRAM SCL (1) For monitoring of additional voltage sources WDI SDA RSTIN1 RST (1) R1 Pushbutton Reset R3 RSTIN2 SQW/FT PFO1 PFI1 R2 To Microprocessor To LED Display To NMI PFO2 PFI2 VSS R4 IRQ/OUT VBAT F32k To INT To 32kHz AI07027 1. Available in SOX28 package only.
Operating modes 2 M41ST87Y, M41ST87W Operating modes The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 160 bytes contained in the device can then be accessed sequentially in the following order: 00h. Tenths/hundredths of a second register 01h. Seconds register 02h. Minutes register 03h. Century/hours register 04h. Day register 05h. Date register 06h. Month register 07h.
M41ST87Y, M41ST87W 2.1 Operating modes 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a clock signal (SCL) and a bidirectional data signal (SDA). The SDA line must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: ● Data transfer may be initiated only when the bus is not busy. ● During data transfer, the data line must remain stable whenever the clock line is high.
Operating modes M41ST87Y, M41ST87W case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 6. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 Figure 7. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCL FROM MASTER 1 DATA OUTPUT BY TRANSMITTER 2 8 MSB 9 LSB DATA OUTPUT BY RECEIVER AI00601 Figure 8.
M41ST87Y, M41ST87W Table 2. Operating modes AC characteristics Parameter(1) Symbol fSCL SCL clock frequency tBUF Time the bus must be free before a new transmission can start tEXPD(2) tF tHD:DAT(3) Min Max Unit 0 400 kHz 1.3 M41ST87Y EX to ECON propagation delay 10 M41ST87W SDA and SCL fall time ns 15 ns 300 ns 0 µs START condition hold time (after this period the first clock pulse is generated) 600 ns tHIGH Clock high period 600 ns tLOW Clock low period 1.
Operating modes Figure 9. M41ST87Y, M41ST87W Slave address location R/W START A 1 LSB MSB SLAVE ADDRESS 1 0 1 0 0 0 AI00602 DATA n+1 ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 10.
M41ST87Y, M41ST87W 2.3 Operating modes WRITE mode In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus protocol is shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer.
Operating modes M41ST87Y, M41ST87W power input is switched from the VCC pin to the battery, and the clock registers and external SRAM are maintained from the attached battery supply. All signal outputs become high impedance. The VOUT pin is capable of supplying 100µA of current to the attached memory with less than 0.3 volts drop under this condition. On power up, when VCC returns to a nominal value, write protection continues for trec by inhibiting ECON.
M41ST87Y, M41ST87W 2.6.2 Operating modes Tamper bits (TB1 and TB2) If the TEBX bit is set, and a tamper condition occurs, the TBX bit will be set to '1.' This bit is “Read-only” and is reset only by setting the TEBX bit to '0.' These bits are located in the flags register 0Fh. 2.6.3 Tamper interrupt enable bits (TIE1 and TIE2) If this bit is set to a logic '1,' the IRQ/OUT pin will be activated when a tamper event occurs.
Operating modes M41ST87Y, M41ST87W Figure 14. Tamper detect connection options TAMPER LO (TPMX = 0) TAMPER HI (TPMX = 1) I. II. VOUT NORMALLY OPEN (TCMX = 1) TPIN III. IV. (2) VCC VOUT TPIN NORMALLY CLOSED (TCMX = 0) (1) TPIN VOUT (Int) (3) TCHI/TCLO = 1 TCHI/TCLO = 0 TCHI/TCLO = 1 TCHI/TCLO = 0 AI07075 Note: These options are summarized in Table 3. 1. If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') during tCLR will not be detected. 2.
M41ST87Y, M41ST87W Operating modes Figure 15.
Operating modes 2.6.6 M41ST87Y, M41ST87W Tamper detect sampling (TDS1 and TDS2) This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input pin(s) to detect a tamper event when the normally closed switch mode is selected. This allows the user to reduce the current drain when the TEBX bit is enabled while the device is in battery backup (see Table 4 on page 23 and Figure 17 on page 23). Sampling is disabled if the TCMX bit is set to logic '1' (Normally Open).
M41ST87Y, M41ST87W Operating modes negative voltage generated by the charge pump during a tamper condition, and from being pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN = logic low). The gates of both MOSFETs should be connected to TPCLR as shown in Figure 20 on page 25. One n-channel enhancement MOSFET should be placed between the output of the inverting charge pump and the VOUT of the M41ST87.
Operating modes M41ST87Y, M41ST87W Figure 18.
M41ST87Y, M41ST87W Table 5. Operating modes Tamper detect timing Symbol Parameter CLRPW 1 CLRPW 0 Min Typ Max Unit tCLRD(1) Tamper RAM clear ext delay X X 1.0(2) 1.5 2.0 ms 0 0 1 s 0 1 4 s 1 0 8 s 1 1 16 s tCLR Tamper clear timing 1. With input capacitance = 70 pF and resistance = 50 Ω. 2. If the OF bit is set, tCLRD(min) = 0.5 ms. Figure 20.
Operating modes 2.7 M41ST87Y, M41ST87W Tamper detection operation The tamper pins are triggered based on the state of an external switch. Two switch mode options are available, normally open or normally closed, based on the setting of the tamper connect mode bit (TCMX). If the selected switch mode is normally open (TCMX = '1'), the tamper pin will be triggered by being connected to VSS (if the TPMX bit is set to '0') or to VCC (if the TPMX bit is set to '1'), through the closing of the external switch.
M41ST87Y, M41ST87W 2.9 Operating modes Internal tamper pull-up/down current Depending on the capacitive and resistive loading of the tamper pin input (TPXIN), the user may require more or less current from the internal pull-up/down used when monitoring the normally closed switch mode. The state of the tamper current hi/tamper current low bit (TCHI/TCLOX) determines the sizing of the internal pull-up/-down.
Operating modes 2.11 M41ST87Y, M41ST87W Tamper event time-stamp Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but the event will also be automatically time-stamped. This is accomplished by freezing the normal update of the clock registers (00h through 07h) immediately following a tamper event.
M41ST87Y, M41ST87W 3 Clock operation Clock operation The eight byte clock register (see Table 7 on page 30) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: A WRITE to any clock register (addresses 0 to 7h) will result in the tenths/hundredths of seconds being reset to “00.
Clock operation 3.1 M41ST87Y, M41ST87W TIMEKEEPER® registers The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm, watchdog, flag, square wave, and tamper data. The 8 clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ TIMEKEEPER cells).
M41ST87Y, M41ST87W Clock operation Keys: 0 = Must be set to zero RB0-RB1 = Watchdog resolution bits 32kE = 32 kHz output enable bit RPT1-RPT5 = Alarm repeat mode bits ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency AF = Alarm flag (read only) S = Sign bit AFE = Alarm flag enable bit SQWE = Square wave enable BL = Battery low flag (read only) SQWOD = Square wave open drain bit BMB0-BMB4 = Watchdog multiplier bits ST = Stop bit CB0-CB1 = Century bits TB (1 and 2) = Tamper
Clock operation M41ST87Y, M41ST87W Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
M41ST87Y, M41ST87W Clock operation Figure 22. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 F –80 = K x (T – TO)2 2 2 K = –0.036 ppm/°C ± 0.006 ppm/°C –100 TO = 25°C ± 5°C –120 –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 Temperature °C AI07888 Figure 23. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 3.3 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings.
Clock operation M41ST87Y, M41ST87W alarm condition activates the IRQ/OUT pin as shown in Figure 25 on page 35. To disable the alarm, write '0' to the alarm date register and to RPT5–RPT1. If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address.
M41ST87Y, M41ST87W Clock operation Figure 25. Backup mode alarm waveform VCC VPFD VSO trec ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/OUT HIGH-Z HIGH-Z AI07087 3.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h.
Clock operation M41ST87Y, M41ST87W Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, either a transition of the WDI pin, or a value of 00h needs to be written to the watchdog register in order to clear the IRQ/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but does not clear the IRQ/OUT pin.
M41ST87Y, M41ST87W 3.6 Clock operation Full-time 32 kHz square wave output The M41ST87Y/W offers the user a special 32 kHz square wave function which defaults to output on the F32k pin (pin 21) as long as VCC ≥ VSO, and the oscillator is running (ST bit = '0'). This function is available within one second (typ) of initial power-up and can only be disabled by setting the 32 kE bit to '0' or the ST bit to '1.' If not used, the F32k pin should be disconnected and allowed to float.
Clock operation M41ST87Y, M41ST87W Table 10. Reset AC characteristics Parameter(1) Symbol tR1 (2) tR2 (2) trec(3) Min Max Unit RSTIN1 low to RST low (min pulse width) 100 200 ns RSTIN2 low to RSTIN2 high (min pulse width) 100 200 ns RSTIN1 or RSTIN2 high to RST high 96 98(3) ms 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. Pulse widths of less than 100 ns will result in no RESET (for noise immunity). 3.
M41ST87Y, M41ST87W 3.11 Clock operation Century bits These two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. Refer to Table 11. These bits represent the next higher order bits of the years register (07h), and should be set accordingly. For example, for the year 2100, they would be set to 1 (D7 = 0 and D6 = 1), and for the year 2300, they would be set to 3 (D7 = 1 and D6 = 1). Once set, they will increment every 100 years.
Clock operation M41ST87Y, M41ST87W The M41ST87Y/W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.
M41ST87Y, M41ST87W Clock operation 3.17 Initial power-on defaults Table 13.
Maximum ratings 4 M41ST87Y, M41ST87W Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 14.
M41ST87Y, M41ST87W 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 15.
DC and AC parameters Table 17. Sym M41ST87Y, M41ST87W DC characteristics Parameter M41ST87Y Test condition(1) Unit Min IBAT(2) Battery current OSC ON Battery current OSC OFF M41ST87W TA = 25 °C, VCC = 0 V, VBAT = 3 V Typ Max 500 700 Min 50 Typ Max 500 700 50 nA nA ICC1 Supply current f = 400 kHz 1.4 0.75 mA ICC2 Supply current (standby) SCL, SDA ≥ VCC – 0.3 V 1 0.
M41ST87Y, M41ST87W Table 17. DC and AC parameters DC characteristics (continued) VSO Battery backup switchover RSW External switch resistance on tamper pin 2.5 2.5 500 V Ω 500 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted). 2. Measured with VOUT and ECON open. Not including tamper detection current (see Table 4 on page 23). 3. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 kΩ resistor.
DC and AC parameters M41ST87Y, M41ST87W Figure 28. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tFB tPD tRB tR trec PFO VALID VALID INPUTS DON'T CARE RECOGNIZED RECOGNIZED RST HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) (1) ECON AI07085 1. ECON available in the SOX28 package only. Table 19.
M41ST87Y, M41ST87W 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 29.
Package mechanical data M41ST87Y, M41ST87W Figure 30. SSOP20 – 20-lead, shrink, small outline package outline 0061436_C Table 21. SSOP20 – 20-lead, shrink, small outline package mechanical data mm in Sym Min Typ A Min Typ 2.000 A1 0.050 A2 1.650 b Max 0.079 0.002 1.850 0.065 0.220 0.380 0.009 0.015 c 0.090 0.250 0.004 0.010 D 6.900 7.200 7.500 0.272 0.283 0.295 E 7.400 7.800 8.200 0.291 0.307 0.323 E1 5.000 5.300 5.600 0.197 0.209 0.220 e L k ddd 1.
M41ST87Y, M41ST87W Package mechanical data Figure 31. Carrier tape for SOX28 package P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 22. Carrier tape dimensions for SOX28 package Package W D SOX28 24.00 ±0.30 1.50 +0.10/ –0.00 E P0 P2 F 1.75 4.00 2.00 11.50 ±0.10 ±0.10 ±0.10 ±0.10 A0 B0 K0 P1 T 12.70 ±0.10 18.20 ±0.10 3.20 ±0.10 16.00 ±0.10 0.30 ±0.05 Unit Bulk Qty mm 1000 Figure 32.
Package mechanical data M41ST87Y, M41ST87W Figure 33. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start 2.5mm min.width AM04928v1 Table 23. Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape (SSOP20 package) A B (max) (min) 24 mm (SOX28) 330 mm (13-inch) 1.5 mm 16 mm (SSOP20) 330 mm (13-inch) 1.5 mm Carrier tape Note: 50/54 D N (min) (min) 13 mm ± 0.2 mm 20.2 mm 60 mm 24.
M41ST87Y, M41ST87W 7 Part numbering Part numbering Table 24. Ordering information scheme Example: M41ST 87Y MX 6 TR Device type M41ST Supply voltage and write protect voltage 87Y(1) = VCC = 4.75 to 5.5 V THS bit = '1': 4.50 V ≤ VPFD ≤ 4.75 V VCC = 4.5 to 5.5 V THS bit = '0': 4.20 V ≤ VPFD ≤ 4.50 V 87W = VCC = 3.0 to 3.6 V; THS bit = '1': 2.80 V ≤ VPFD ≤ 3.00 V VCC = 2.7 to 3.6 V; THS bit = '0': 2.55 V ≤ VPFD ≤ 2.
References 8 M41ST87Y, M41ST87W References KDS, the crystal component supplier mentioned in this document, can be contacted at kouhou@kdsj.co.jp or http://www.kds.info/index_en.
M41ST87Y, M41ST87W 9 Revision history Revision history Table 25. Document revision history Date Revision Changes May-2002 1 First issue. 23-Apr-2003 2 Document promoted to preliminary data. 10-Jul-2003 2.1 Update tamper information ( Figure 4, 5, 14, 15, 16; Table 17, 4, 12). 11-Sep-2003 2.2 Update electrical, charge pump, and clock information (Table 17; Figure 5, 19, 20). 15-Jun-2004 3 Reformatted; added lead-free information; updated characteristics (Figure 2; Table 1, 14, 17, 24).
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