Datasheet

M41ST87Y, M41ST87W Clock operation
Doc ID 9497 Rev 10 41/54
3.17 Initial power-on defaults
Note: All other control bits are undetermined.
Table 13. Default values
Condition TR ST OF OFIE HT
(1)
Out FT AFE
Initial power-up 0 0 1 0 1 1 0 0
Subsequent power-up (with
battery backup)
(2)(3)
UC UC UC 0 ⇑ 1 ⇓ UC 0 ⇓ 0 ⇑
Condition ABE SQWE SQWOD PFOD Watchdog register
(4)
Initial power-up 0 0 1 1 0
Subsequent power-up (with
battery backup)
(2)(3)
0 ⇑ 0 ⇑ UC UC 0 ⇓
Condition 32kE THS TEB1 and 2 TCM1 and 2 TPM1 and 2 TDS1 and 2
Initial power-up 1
(5)
00 0 0 0
Subsequent power-up (with
battery backup)
(2)
UC UC UC UC UC UC
Condition
TCHI/TCLO1
and 2
CLR1
and 2
TIE1 and 2 CLRPW0 CLRPW1
CLR1
EXT
and
CLR2
EXT
Initial power-up 0 0 0 0 0 0
Subsequent power-up (with
battery backup)
(2)
UC UC 0 ⇑ UC UC UC
1. When TEB
X
is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence).
2. UC = unchanged.
3. ⇑ = V
CC
rising; ⇓ = V
CC
falling.
4. WDS, BMB0-BMB4, RB0, RB1.
5. 32 kHz output valid only on V
CC
.