Datasheet

M41ST87Y, M41ST87W Operating modes
Doc ID 9497 Rev 10 15/54
Table 2. AC characteristics
2.2 READ mode
In this mode the master reads the M41ST87Y/W slave after setting the slave address (see
Figure 9 on page 16). Following the WRITE mode control bit (R/W
=0) and the acknowledge
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W
=1). At this
point the master transmitter becomes the master receiver.
The data byte which was addressed will be transmitted and the master receiver will send an
acknowledge bit to the slave transmitter. The address pointer is only incremented on
reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the
data byte at address An+1 on the bus, the master receiver reads and acknowledges the new
byte and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter (see Figure 10 on page 16).
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to a non-clock or RAM address.
Note: This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 11 on page 16).
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).
Min Max Unit
f
SCL
SCL clock frequency 0 400 kHz
t
BUF
Time the bus must be free before a new transmission can start 1.3 µs
t
EXPD
(2)
2. Available in SOX28 package only.
EX to E
CON
propagation delay
M41ST87Y 10 ns
M41ST87W 15 ns
t
F
SDA and SCL fall time 300 ns
t
HD:DAT
(3)
3. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
Data hold time 0 µs
t
HD:STA
START condition hold time
(after this period the first clock pulse is generated)
600 ns
t
HIGH
Clock high period 600 ns
t
LOW
Clock low period 1.3 µs
t
R
SDA and SCL rise time 300 ns
t
SU:DAT
Data setup time 100 ns
t
SU:STA
START condition setup time
(only relevant for a repeated start condition)
600 ns
t
SU:STO
STOP condition setup time 600 ns