Datasheet

Clock operation M41ST85W
28/43 Doc ID 7531 Rev 11
3.13 t
rec
bit
Bit D7 of clock register 04h contains the t
rec
bit (TR). t
rec
refers to the automatic
continuation of the deselect time after V
CC
reaches V
PFD
. This allows for a voltage settling
time before WRITEs may again be performed to the device after a power-down condition.
The t
rec
bit will allow the user to set the length of this deselect time as defined by Ta bl e 6 .
3.14 Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state:
watchdog register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state:
ST, OUT, and HT (see Ta ble 7).
Table 6. t
rec
definitions
Table 7. Default values
t
rec
bit (TR) STOP bit (ST)
t
rec
time
Units
Min Max
009698ms
0140200
(1)
1. Default setting
ms
1 X 50 2000 µs
Condition TR ST HT Out FT AFE ABE SQWE
Watchdog
register
(1)
1. WDS, BMB0-BMB4, RB0, RB1.
Initial power-up
(2)
2. State of other control bits undefined.
0111000 0 0
Subsequent power-up
(with battery backup)
(3)
3. UC = Unchanged
UC UC 1 UC 0 0 0 0 0