Datasheet

Clock operation M41ST85W
26/43 Doc ID 7531 Rev 11
3.8 Reset inputs (RSTIN1 & RSTIN2)
The M41ST85W provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Table 5 and Figure 17 illustrate the AC reset characteristics of this function. Pulses shorter
than t
RLRH1
and t
RLRH2
will not generate a reset condition. RSTIN1 and RSTIN2 are each
internally pulled up to V
CC
through a 100 kΩ resistor.
Figure 17. RSTIN1
& RSTIN2 timing waveforms
Note: With pull-up resistor
Table 5. Reset AC characteristics
3.9 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (1.25 V). If PFI is less
than the power-fail threshold (V
PFI
), the power-fail output (PFO) will go low. This function is
intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is
connected through an external voltage divider (see Figure 5 on page 11) to either the
unregulated DC input (if it is available) or the regulated output of the V
CC
regulator. The
voltage divider can be set up such that the voltage at PFI falls below V
PFI
several
milliseconds before the regulated V
CC
input to the M41ST85W or the microprocessor drops
below the minimum operating voltage.
During battery backup, the power-fail comparator turns off and PFO
goes (or remains) low.
This occurs after V
CC
drops below V
PFD
(min). When power returns, PFO is forced high,
irrespective of V
PFI
for the write protect time (t
rec
), which is the time from V
PFD
(max) until the
inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 3.6 V (except where noted).
Min Max Unit
t
RLRH1
(2)
2. Pulse width less than 50 ns will result in no RESET (for noise immunity).
RSTIN1 low to RSTIN1 high 200 ns
t
RLRH2
(3)
3. Pulse width less than 20 ms will result in no RESET (for noise immunity).
RSTIN2 low to RSTIN2 high 100 ms
t
R1HRH
(4)
4. Programmable (see Table 6 on page 28).
RSTIN1 high to RST high 40 200 ms
t
R2HRH
(4)
RSTIN2 high to RST high 40 200 ms
AI03665
RSTIN2
RST
(1)
RSTIN1
tRLRH1
tRLRH2
tR1HRH tR2HRH