Datasheet

M41ST85W Clock operation
Doc ID 7531 Rev 11 25/43
pin. This will also disable the watchdog function until it is again programmed correctly. A
READ of the flags register will reset the watchdog flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared. If the watchdog function is set to output to the IRQ
/FT/OUT pin and the frequency
test function is activated, the watchdog function prevails and the frequency test function is
denied.
3.6 Square wave output
The M41ST85W offers the user a programmable square wave function which is output on
the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency.
These frequencies are listed in Tab le 4. Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 0Ah.
Table 4. Square wave output frequency
3.7 Power-on reset
The M41ST85W continuously monitors V
CC
. When V
CC
falls to the power fail detect trip
point, the RST
pulls low (open drain) and remains low on power-up for t
rec
after V
CC
passes
V
PFD
(max). The RST pin is an open drain output and an appropriate pull-up resistor should
be chosen to control rise time.
Square wave bits Square wave
RS3 RS2 RS1 RS0 Frequency Units
0000None–
000132.768kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz