Datasheet

Operating modes M41ST85W
14/43 Doc ID 7531 Rev 11
Figure 6. Serial bus data transfer sequence
Figure 7. Acknowledgement sequence
Figure 8. Write cycle timing: RTC & external SRAM control signals
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
AI03663
EX
E
CON
tEXPD
tEXPD