M41ST85W 3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features SNAPHAT battery & crystal ■ Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM (LPSRAM) ■ 400 kHz I2C serial interface ■ 3.0/3.3 V operating voltage – VCC = 2.7 to 3.
Contents M41ST85W Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 Start data transfer . . .
M41ST85W Contents 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of tables M41ST85W List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/43 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M41ST85W List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 28-pin SOIC connections . . . . . . . . . .
Description 1 M41ST85W Description The M41ST85W is a combination serial real-time clock, microprocessor supervisor, and NVRAM supervisor. It is built in a low-power CMOS SRAM process and has a 64-byte memory space with 44 bytes of NVRAM and 20 memory-mapped RTC registers (see Table 2 on page 20). The RTC registers are configured in binary coded decimal (BCD) format.
M41ST85W Description M4T28-BR12SH1 (48 mAh) and M4T32-BR12SH1 (120 mAh). For the extended temperature requirement, the 120 mAh M4T32-BR12SH6 is available. For more information, see Table 21 on page 40. Caution: Do not place the SNAPHAT® battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. The 300 mil SOX embedded crystal SOIC typically requires a user-supplied battery for nonvolatile operation. Capacitor backup can also be implemented with this package. Figure 1.
Description M41ST85W Table 1.
M41ST85W Description Figure 3. 28-pin, 300 mil SOIC connections NF NF NF NF NC NC NC SQW WDI RSTIN1 RSTIN2 PFO NC VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M41ST85W 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC EX IRQ/FT/OUT VOUT NC PFI SCL NC NC RST NC SDA ECON VBAT AI06370d Note: No function (NF) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally shorted together.
Description Figure 4. M41ST85W Block diagram REAL TIME CLOCK CALENDAR SDA 44 BYTES USER RAM I2C INTERFACE RTC w/ALARM & CALIBRATION SCL (2) Crystal WATCHDOG 32KHz OSCILLATOR SQUARE WAVE WDI VCC AFE WDS IRQ/FT/OUT(1) SQW VOUT VBAT VBL= 2.5V COMPARE VSO = 2.5V COMPARE VPFD = 2.65V COMPARE BL POR RST(1) RSTIN1 RSTIN2 ECON EX PFI COMPARE PFO 1.25V (Internal) AI03932 1. Open drain output. 2. Crystal integrated into SOIC package for MX package option.
M41ST85W Figure 5. Description Hardware hookup M41ST85W Regulator Unregulated Voltage VIN VCC VCC VOUT VCC ECON E EX LPSRAM From MCU SCL R1 SDA WDI Pushbutton Reset RSTIN1 RST RSTIN2 SQW To RST To LED Display PFO To NMI (1) IRQ/FT/OUT VBAT To INT PFI R2 VSS AI03660 1. Required for embedded crystal (MX) package only.
Operating modes 2 M41ST85W Operating modes The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/hundredths of a second register 2. Seconds register 3. Minutes register 4. Century/hours register 5. Day register 6. Date register 7. Month register 8. Year register 9.
M41ST85W Operating modes Accordingly, the following bus conditions have been defined: 2.1.1 Bus not busy Both data and clock lines remain high. 2.1.2 Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. 2.1.3 Stop data transfer A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition. 2.1.
Operating modes Figure 6. M41ST85W Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 Figure 7. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER 1 2 8 MSB 9 LSB DATA OUTPUT BY RECEIVER AI00601 Figure 8.
M41ST85W 2.2 Operating modes Read mode In this mode the master reads the M41ST85W slave after setting the slave address (see Figure 9). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver.
Operating modes M41ST85W SLAVE ADDRESS DATA n+1 ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 10. Read mode sequence STOP SLAVE ADDRESS DATA n+X P NO ACK AI00899 STOP R/W SLAVE ADDRESS 16/43 DATA n+X P NO ACK BUS ACTIVITY: DATA n+1 ACK DATA n ACK S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 11.
M41ST85W 2.3 Operating modes Write mode In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol is shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer.
Operating modes M41ST85W If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use.
M41ST85W 3 Clock operation Clock operation The eight byte clock register (see Table 2 on page 20) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Note: A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to “00,” and tenths/hundredths of seconds cannot be written to any value other than “00.
Clock operation M41ST85W TIMEKEEPER® register map Table 2. Data Function/range Address D7 D6 00h D5 D4 D3 D2 0.1 seconds D1 BCD format D0 0.
M41ST85W 3.3 Clock operation Calibrating the clock The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +/–1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes with temperature (see Figure 13 on page 22).
Clock operation M41ST85W Figure 13. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 ΔF = K x (T – T )2 O F –80 2 2 K = –0.036 ppm/°C ± 0.006 ppm/°C –100 TO = 25°C ± 5°C –120 –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 Temperature °C AI07888 Figure 14.
M41ST85W 3.4 Clock operation Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41ST85W is in the battery backup to serve as a system wake-up call. Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Table 3 shows the possible configurations.
Clock operation M41ST85W Figure 16. Backup mode alarm waveform VCC VPFD VSO trec ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT HIGH-Z HIGH-Z AI03920 3.5 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h.
M41ST85W Clock operation pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. 3.
Clock operation 3.8 M41ST85W Reset inputs (RSTIN1 & RSTIN2) The M41ST85W provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 5 and Figure 17 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100 kΩ resistor. Figure 17.
M41ST85W Clock operation follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. 3.10 Century bit Bits D7 and D6 of clock register 03h contain the Century Enable bit (CEB) and the Century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. 3.
Clock operation 3.13 M41ST85W trec bit Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs may again be performed to the device after a power-down condition. The trec bit will allow the user to set the length of this deselect time as defined by Table 6. 3.
M41ST85W 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC parameters 5 M41ST85W DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9.
M41ST85W Table 11. DC and AC parameters DC characteristics Sym Parameter M41ST85W Test condition(1) Unit Min IBAT(2) ICC1 ICC2 ILI(3) ILO(4) IOUT1(5) IOUT2 Battery current OSC ON Battery current OSC OFF Supply current Supply current (standby) Input leakage current TA = 25°C, VCC = 0 V, VBAT = 3 V Typ Max 400 500 nA 50 nA f = 400 kHz 0.75 mA SCL, SDA = VCC – 0.3 V or VSS + 0.3 V 0.
DC and AC parameters M41ST85W Figure 19. Bus timing requirements sequence SDA tBUF tHD:STA tHD:STA tR tF SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR tSU:STO P AI00589 Table 12. AC characteristics Parameter(1) Symbol fSCL SCL clock frequency tBUF Time the bus must be free before a new transmission can start tEXPD EX to ECON propagation delay tF tHD:DAT(2) Min Max Unit 0 400 kHz 1.
M41ST85W DC and AC parameters Figure 20. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tRB tDR tPD trec PFO INPUTS DON'T CARE RECOGNIZED RECOGNIZED RST HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) ECON AI03661 Table 13.
Package mechanical data 6 M41ST85W Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 21.
M41ST85W Package mechanical data Figure 22. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. 4-pin SNAPHAT® housing for 48 mAh battery & crystal, mechanical data millimeters inches Symbol Typ Min A Max Typ Min 9.78 Max 0.3850 A1 6.73 7.24 0.2650 0.2850 A2 6.48 6.99 0.2551 0.2752 A3 0.38 0.0150 B 0.46 0.56 0.0181 0.0220 D 21.21 21.84 0.8350 0.8598 E 14.22 14.99 0.
Package mechanical data M41ST85W Figure 23. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. 4-pin SNAPHAT® housing for 120 mAh battery & crystal, mechanical data millimeters inches Symbol Typ Min A Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 36/43 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.
M41ST85W Package mechanical data Figure 24. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, package outline D 14 h x 45° 1 C E 15 H 28 A2 A B ddd A1 e A1 α L SO-E Note: Drawing is not to scale. Table 17. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data millimeters inches Symbol Typ Min Max A 2.44 A1 Min Max 2.69 0.096 0.106 0.15 0.31 0.006 0.012 A2 2.29 2.39 0.090 0.094 B 0.41 0.51 0.016 0.020 C 0.20 0.
Package mechanical data M41ST85W Figure 25. Carrier tape for SOH28 and SOX28 package P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 18. Carrier tape dimensions for SOH28 and SOX28 packages Package W D SOH28 24.00 ±0.30 1.50 +0.10/ –0.00 SOX28 24.00 ±0.30 1.50 +0.10/ –0.00 38/43 A0 B0 K0 P1 T Unit Bulk Qty 1.75 4.00 2.00 11.50 ±0.10 ±0.10 ±0.10 ±0.10 12.90 ±0.10 18.70 ±0.10 3.20 ±0.10 16.00 ±0.10 0.30 ±0.
M41ST85W Package mechanical data Figure 26. Reel schematic T 40mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start 2.5mm min.width AM04928v1 Table 19. Reel dimensions for 24 mm carrier tape (SOH28 and SOX28 packages) Carrier tape 24 mm (SOH28, SOX28) Note: A B (max) (min) 330 mm (13-inch) 1.5 mm C 13 mm ± 0.2 mm D N (min) (min) 20.2 mm 60 mm G 24.4 mm + 2/–0 mm T (max) 30.
Part numbering 7 M41ST85W Part numbering Table 20. Ordering information scheme Example: M41ST 85W MH 6 E Device type M41ST Supply voltage and write protect voltage 85W = VCC = 2.7 to 3.6 V; 2.55V ≤ VPFD ≤ 2.70 V Package MH(1) = SOH28 MX(2) = SOX28 Temperature range 6 = –40 to 85°C Shipping method For SOH28: E = ECOPACK® package, tubes(3) F = ECOPACK® package, tape & reel For SOX28: Blank = ECOPACK® package, tubes(3) TR = ECOPACK® package, tape & reel 1.
M41ST85W 8 Environmental information Environmental information Figure 27. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
Revision history M41ST85W 9 Revision history Table 22. Document revision history Date Revision Aug-2000 1 Changes First issue 24-Aug-2000 1.1 Block diagram added (Figure 4) 12-Oct-2000 1.2 trec table removed, cross references corrected 18-Dec-2000 2 Reformatted, TOC added, and PFI input leakage current added (Table 11) 18-Jun-2001 2.
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