Datasheet

Operation M40SZ100W
8/20 DocID007528 Rev 4
2 Operation
The M40SZ100W, as shown in Figure 4 on page 7, can control one (two, if placed in
parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable
input disable all other input signals. Most slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal operating conditions, the conditioned
chip enable (E
CON
) output pin follows the chip enable (E) input pin with timing shown in
Table 2 on page 10. An internal switch connects V
CC
to V
OUT
. This switch has a voltage
drop of less than 0.3 V (I
OUT1
).
When V
CC
degrades during a power failure, E
CON
is forced inactive independent of E. In
this situation, the SRAM is unconditionally write protected as V
CC
falls below an out-of-
tolerance threshold (V
PFD
). For the M40SZ100W the power fail detection value associated
with V
PFD
is shown in Table 7 on page 16.
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time t
WPT
, E
CON
is unconditionally driven high, write protecting the SRAM.
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the SRAM's contents. At voltages below V
PFD
(min), the
user can be assured the memory will be write protected within the Write Protect Time (t
WPT
)
provided the V
CC
fall time does not exceed t
F
(see Table 2 on page 10).
As V
CC
continues to degrade, the internal switch disconnects V
CC
and connects the internal
battery to V
OUT
. This occurs at the switchover voltage (V
SO
). Below the V
SO
, the battery
provides a voltage V
OHB
to the SRAM and can supply current I
OUT2
(see Table 7 on
page 16).
When V
CC
rises above V
SO
, V
OUT
is switched back to the supply voltage. Output E
CON
is
held inactive for t
CER
(120 ms maximum) after the power supply has reached V
PFD
,
independent of the E input, to allow for processor stabilization (see Figure 6 on page 10).
2.1 Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40SZ100W NVRAM
controller. There are, however some criteria which should be used in making the final choice
of which SRAM to use. The SRAM must be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows inputs to the M40SZ100W and SRAMs to
be “Don't care” once V
CC
falls below V
PFD
(min) (see Figure 5 on page 9). The SRAM should
also guarantee data retention down to V
CC
= 2.0 V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the I
CCDR
value of
the M40SZ100W to determine the total current requirements for data retention.
Caution: Take care to avoid inadvertent discharge through V
OUT
and E
CON
after battery has been
attached.