Datasheet

Operation M40SZ100W
12/20 DocID007528 Rev 4
If a battery low is generated during a power-up sequence, this indicates that the battery is
below 2.5 V and may not be able to maintain data integrity in the SRAM. Data should be
considered suspect, and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
CC
is supplied. In order to insure data integrity during subsequent periods of
battery back-up mode, the battery should be replaced.
The M40SZ100W only monitors the battery when a nominal V
CC
is applied to the device.
Thus applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique. The BL pin is an open drain output and an
appropriate pull-up resistor to V
CC
should be chosen to control the rise time.
2.5 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V
PFD
comparator). If PFI is less than the power-fail threshold (V
PFI
), the power-fail
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 4 on page 7) to either the unregulated DC input (if it is available) or the
regulated output of the V
CC
regulator. The voltage divider can be set up such that the
voltage at PFI falls below V
PFI
several milliseconds before the regulated V
CC
input to the
M40SZ100W or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator turns off and PFO goes (or remains) low.
This occurs after V
CC
drops below V
PFD
(min). When power returns, PFO is forced high,
irrespective of V
PFI
for the write protect time (t
REC
), which is the time from V
PFD
(max) until
the inputs are recognized. At the end of this time, the power-fail comparator is enabled and
PFO follows PFI. If the comparator is unused, PFI should be connected to V
SS
and PFO left
unconnected.
2.6 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 μF (as shown in
Figure 8 on page 13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.