Datasheet

Instructions M24M02-DR
14/36 DocID18204 Rev 6
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for
the data byte.
The 256 Kbytes (2 Mb) are addressed with 18 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bits (A17, A16) being
included in the Device Select code (see Ta b l e 4).
When the bus master generates a Stop conditio
n immediately after a data byte Ack bit (in
the “10
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t
W
is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful co
mpletion of an internal Write cycle (t
W
), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disab
led internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, th
e Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
Table 3. Most significant address byte
A15 A14 A13 A12 A11 A10 A9 A8
Table 4. Least significant address byte
A7 A6 A5 A4 A3 A2 A1 A0