M24M02-DR 2-Mbit serial I²C bus EEPROM Datasheet - production data Features SO8 (MN) 150 mil width WLCSP • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz • Memory array: – 2 Mbit (256 Kbytes) of EEPROM – Page size: 256 bytes – Additional Write lockable page • Single supply voltage: – 1.8 V to 5.
Contents M24M02-DR Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2) . . . .
M24M02-DR Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . .
List of tables M24M02-DR List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. 4/36 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Most significant address byte . . .
M24M02-DR List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO8 connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 WLCSP connections . . . .
Description 1 M24M02-DR Description The M24M02-DR is a 2 Mb I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 256 K × 8 bits. The M24M02-DR can operate with a supply voltage from 1.8 V to 5.5 V, over an ambient temperature range of –40 °C / +85 °C. The M24M02-DR offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1.
M24M02-DR Description Figure 3. WLCSP connections E2 DU DU DU Vss E2 DU Vss SDA SDA WC Vcc Vcc SCL WC SCL Bump side view Top view (bumps underneath) MS30979V2 1. DU: Don't Use (must be left floating) 2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Signal description M24M02-DR 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
M24M02-DR Signal description 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
Memory organization 3 M24M02-DR Memory organization The memory is organized as shown below. Figure 5.
M24M02-DR 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
Device operation 4.1 M24M02-DR Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
M24M02-DR 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2. Device select code Chip Enable Device type identifier(1) Device select code b7 1 b6 0 b5 1 b4 0 b3 (2) E2 MSB address bits RW b2 b1 b0 A17 A16 RW 1.
Instructions M24M02-DR 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 4.
M24M02-DR Byte Write After the device select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7.
Instructions 5.1.2 M24M02-DR Page Write The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A17/A8, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
M24M02-DR 5.1.3 Instructions Write Identification Page The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: • Device type identifier = 1011b • MSB address bits A17/A8 are don't care except for address bit A10 which must be ‘0’.
Instructions 5.1.6 M24M02-DR Minimizing Write delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.
M24M02-DR Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
Instructions 5.2.1 M24M02-DR Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.
M24M02-DR 5.4 Initial delivery state Read the lock status The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.
Maximum rating 7 M24M02-DR Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max.
M24M02-DR 8 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C Max. Unit Table 7. AC measurement conditions Symbol Cbus Parameter Min. Load capacitance 100 SCL input rise/fall time, SDA input fall time - pF 50 ns Input levels 0.2 VCC to 0.
DC and AC parameters M24M02-DR Table 9. Cycling performance by groups of four bytes Symbol Ncycle Parameter Write cycle endurance(1) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(2) 1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification. 2.
M24M02-DR DC and AC parameters . Table 11. DC characteristics Symbol Test conditions (in addition to those in Table 6 and Table 7) Parameter Min. Max. Unit ILI Input leakage current (E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 1 mA VCC = 2.5 V, fc =400 kHz - 1 mA VCC = 5.5 V, fc =400 kHz - 2 mA 1.8 V < VCC < 5.5 V, fc= 1 MHz - 2.
DC and AC parameters M24M02-DR Table 12. 400 kHz AC characteristics Parameter(1) Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(2) tF tXH1XH2 tR Min. Max.
M24M02-DR DC and AC parameters Table 13. 1 MHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tXH1XH2 tXL1XL2 tQL1QL2(2) Min. Max.
DC and AC parameters M24M02-DR Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (k ) 100 10 4k The R bus x Cbustime constant must be below the 400 ns time constant line represented on the left. R bu s × C bu s = Here Rbus × Cbus = 120 ns 40 VCC Rbus 0n s I²C bus master SCL M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Figure 13.
M24M02-DR DC and AC parameters Figure 14.
Package mechanical data 9 M24M02-DR Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
M24M02-DR Package mechanical data Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A – – 1.750 – – 0.0689 A1 – 0.100 0.250 – 0.0039 0.0098 A2 – 1.250 – – 0.0492 – b – 0.280 0.480 – 0.0110 0.
Package mechanical data M24M02-DR Figure 16. M24M02-DR WLCSP package outline, bump side view D e1 A1 e e2 e3 E A A2 Side view Bump side E1_ME_V1 1. Drawing is not to scale. Table 15. M24M02-DR WLCSP package mechanical data(1) inches(2) millimeters Symbol Min Typ Max Min Typ Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 - - 0.0075 - - A2 0.350 - - 0.0138 - - B (ball diameter) 0.270 - - 0.0106 - - D 3.536 3.556 3.576 0.1392 0.1400 0.1408 E 1.
M24M02-DR Package mechanical data Figure 17. M24M02-DR WLCSP recommended footprint 2.100 mm ø 0.270 mm 1.000 mm 0.500 mm 1.200 mm 0.
Part numbering 10 M24M02-DR Part numbering Table 16. Ordering information scheme Example: M24M02 - D R MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function M02-D = 2 Mbit (256 Kb × 8 bits) EEPROM with additional identification page Operating voltage R = VCC = 1.8 V to 5.
M24M02-DR 11 Revision history Revision history Table 17. Document revision history Date Revision 22-Dec-2010 1 Initial release. 09-Feb-2011 2 Updated: – Section 3.18: Read Identification Page – Section 3.
M24M02-DR Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.
