Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsIntegrated Circuits (ICs)SOIC 8 1024 kBit 128 K x 8

This is information on a product in full production.

September 2012 Doc ID 12943 Rev 10 1/38

M24M01-R M24M01-DF

1-Mbit serial I²C bus EEPROM

Datasheet − production data

Features

■ Compatible with all I

C bus modes:

–1 MHz

– 400 kHz

– 100 kHz

■ Memory array:

– 1 Mbit (128 Kbytes) of EEPROM

– Page size: 256 bytes

– Additional Write lockable page

(M24M01-D order codes)

■ Single supply voltage and high speed:

– 1 MHz clock from 1.7 V to 5.5 V

■ Write:

– Byte Write within 5 ms

– Page Write within 5 ms

■ Operating temperature range: from -40 °C up

to +85 °C

■ Random and sequential Read modes

■ Write protect of the whole memory array

■ Enhanced ESD/Latch-Up protection

■ More than 4 million Write cycles

■ More than 200-year data retention

■ Packages:

– RoHS compliant and halogen-free

(ECOPACK

)

SO8 (MN)

150 mil width

TSSOP8 (DW)

WLCSP (CS)

www.st.com

Summary of content (38 pages)

PAGE 1
M24M01-R M24M01-DF 1-Mbit serial I²C bus EEPROM Datasheet − production data Features ■ Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz ■ Memory array: – 1 Mbit (128 Kbytes) of EEPROM – Page size: 256 bytes – Additional Write lockable page (M24M01-D order codes) ■ Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.
PAGE 2
Contents M24M01-R M24M01-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
PAGE 3
M24M01-R M24M01-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
List of tables M24M01-R M24M01-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. 4/38 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
M24M01-R M24M01-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
Description 1 M24M01-R M24M01-DF Description The M24M01 is a 1 Mb I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 128 K × 8 bits. The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of –40 °C / +85 °C. The M24M01-D offers an additional page, named the Identification Page (256 bytes).
PAGE 7
M24M01-R M24M01-DF Figure 2. Description 8-pin package connections $5 % % 633 6## 7# 3#, 3$! -3 6 1. DU: Don't Use (if connected, must be connected to VSS) 2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1. Figure 3. WLCSP connections for M24M01 DFCS6TP/K (top view, marking side, with balls on the underside) VCC SDA SCL E2 WC E1 VSS DU MS30966V2 3. DU: Don't Use (if connected, must be connected to VSS) 4.
PAGE 8
Signal description M24M01-R M24M01-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
PAGE 9
M24M01-R M24M01-DF Signal description 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).
PAGE 10
Memory organization 3 M24M01-R M24M01-DF Memory organization The memory is organized as shown below. Figure 5.
PAGE 11
M24M01-R M24M01-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
PAGE 12
Device operation 4.1 M24M01-R M24M01-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
PAGE 13
M24M01-R M24M01-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2.
PAGE 14
Instructions M24M01-R M24M01-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. A15 Table 4.
PAGE 15
M24M01-R M24M01-DF Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7.
PAGE 16
Instructions 5.1.2 M24M01-R M24M01-DF Page Write The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
PAGE 17
M24M01-R M24M01-DF 5.1.3 Instructions Write Identification Page (M24M01-D only) The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction.
PAGE 18
Instructions 5.1.5 M24M01-R M24M01-DF ECC (Error Correction Code) and Write cycling The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(a). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved.
PAGE 19
M24M01-R M24M01-DF 5.1.6 Instructions Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: ● Initial condition: a Write cycle is in progress. ● Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
PAGE 20
Instructions 5.2 M24M01-R M24M01-DF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
PAGE 21
M24M01-R M24M01-DF 5.2.1 Instructions Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.
PAGE 22
Initial delivery state 5.4 M24M01-R M24M01-DF Read the lock status (M24M01-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.
PAGE 23
M24M01-R M24M01-DF 7 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min.
PAGE 24
DC and AC parameters 8 M24M01-R M24M01-DF DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range R) Symbol Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.7 5.
PAGE 25
M24M01-R M24M01-DF Table 10. Symbol Ncycle DC and AC parameters Cycling performance by groups of four bytes Parameter Write cycle endurance(2) Test condition(1) Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(3) 1. Cycling performance for products identified by process letter K. 2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
PAGE 26
DC and AC parameters . Table 12. Symbol M24M01-R M24M01-DF DC characteristics (M24M01-R, device grade 6) Test conditions (in addition to those in Table 6) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA VCC = 1.8 V, fc= 400 kHz 1(1) mA VCC = 2.5 V, fc =400 kHz 1 mA VCC = 5.5 V, fc =400 kHz 1.5(2) mA fc= 1 MHz 1.
PAGE 27
M24M01-R M24M01-DF Table 13. Symbol DC and AC parameters DC characteristics (M24M01-F, device grade 6) Test conditions (in addition to those in Table 6) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA VCC = 1.7 V, fc= 400 kHz 1 mA VCC = 2.5 V, fc =400 kHz 1 mA VCC = 5.5 V, fc =400 kHz 1.5 mA fc= 1 MHz 1.
PAGE 28
DC and AC parameters Table 14. M24M01-R M24M01-DF 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max.
PAGE 29
M24M01-R M24M01-DF Table 15. DC and AC parameters 1 MHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tXH1XH2 tXL1XL2 tQL1QL2 (8) Parameter Min. Max.
PAGE 30
DC and AC parameters M24M01-R M24M01-DF Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz "US LINE PULL UP RESISTOR K K½ 4HE 2 BUS X #BUS TIME CONSTANT MUST BE BELOW THE NS TIME CONSTANT LINE REPRESENTED ON THE LEFT 2 BU S § # BU S (ERE 2BUS § #BUS NS 6## 2BUS N S )£# BUS MASTER 3#, - XXX 3$! P& "US LINE CAPACITOR P& #BUS AI B Figure 13.
PAGE 31
M24M01-R M24M01-DF DC and AC parameters Figure 14.
PAGE 32
Package mechanical data 9 M24M01-R M24M01-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 16.
PAGE 33
M24M01-R M24M01-DF Package mechanical data Figure 16. SO8N – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 17. SO8N – 8 lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min A Max Typ Min 1.750 Max 0.0689 A1 0.100 A2 1.250 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.250 0.0039 0.
PAGE 34
Package mechanical data M24M01-R M24M01-DF Figure 17. M24M01 DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline BBB : $ E 9 8 E $ETAIL ! % & ! ! 8 7AFER BACK SIDE E E AAA 2EFERENCE & ' ' /RIENTATION "UMPS SIDE 3IDE VIEW "UMP ! EEE : B CCC DDD 3EATING PLANE - : 89 - : $ETAIL ! 2OTATED 1. Drawing is not to scale.
PAGE 35
M24M01-R M24M01-DF Table 18. Package mechanical data M24M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 0.0075 A2 0.350 0.0138 b 0.270 0.0106 D 2.560 2.580 0.1008 0.1016 E 1.698 1.718 0.0669 0.0676 e 1.000 0.0394 e1 0.866 0.0341 e2 0.500 0.0197 e3 0.500 0.0197 F 0.416 0.0164 G 0.780 0.0307 8 8 aaa 0.110 0.0039 bbb 0.
PAGE 36
Part numbering 10 M24M01-R M24M01-DF Part numbering Table 19. Ordering information scheme Example: M24M01 - D R MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function M01 = 1 Mbit (128 Kb × 8 bits) Device family Blank: Without Identification page D: With additional Identification page Operating voltage R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
PAGE 37
M24M01-R M24M01-DF 11 Revision history Revision history Table 20. Document revision history Date 02-May-2011 23-Apr-2012 26-Sep-2012 Revision Changes 8 Updated Features on page 1. Updated Figure 3: WLCSP8 connections (bumps side view), Figure 5: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz and Figure 6: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz.
PAGE 38
M24M01-R M24M01-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.