Datasheet

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This is information on a product in full production.

November 2013 DocID16891 Rev 28 1/42

M24C64-W M24C64-R M24C64-F

M24C64-DF

64-Kbit serial I²C bus EEPROM

Datasheet - production data

Features

 Compatible with all I

C bus modes:

–1 MHz

– 400 kHz

– 100 kHz

 Memory array:

– 64 Kbit (8 Kbytes) of EEPROM

– Page size: 32 bytes

– Additional Write lockable page 

(M24C64-D order codes)

 Single supply voltage:

– 1.7 V to 5.5 V over –40 °C / +85 °C

 Write:

– Byte Write within 5 ms

– Page Write within 5 ms

 Random and sequential Read modes

 Write protect of the whole memory array

 Enhanced ESD/Latch-Up protection

 More than 4 million Write cycles

 More than 200-year data retention

 Packages:

– RoHS compliant and halogen-free

(ECOPACK

)

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8

(MC)

WLCSP (CS)

Thin WLCSP (CT)

www.st.com

Summary of content (42 pages)

PAGE 1
M24C64-W M24C64-R M24C64-F M24C64-DF 64-Kbit serial I²C bus EEPROM Datasheet - production data Features  Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width  Memory array: – 64 Kbit (8 Kbytes) of EEPROM – Page size: 32 bytes – Additional Write lockable page  (M24C64-D order codes)  Single supply voltage: – 1.7 V to 5.
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M24C64-W M24C64-R M24C64-F  Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
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M24C64-W M24C64-R M24C64-F  5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . .
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M24C64-W M24C64-R M24C64-F  List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. 4/42 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . .
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M24C64-W M24C64-R M24C64-F  List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M24C64-W M24C64-R M24C64-F  Description 1 Description The M24C64 is a 64-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 8 K × 8 bits. The M24C64-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C64-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
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M24C64-W M24C64-R M24C64-F  Figure 3. 5-bump WLCSP connections (top view) VSS VCC SDA WC SCL MS18655V3 Note: Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further explanations. Figure 4.
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M24C64-W M24C64-R M24C64-F  Signal description 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
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M24C64-W M24C64-R M24C64-F  2.5 VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).
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M24C64-W M24C64-R M24C64-F  Memory organization 3 Memory organization The memory is organized as shown below. Figure 6.
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M24C64-W M24C64-R M24C64-F  4 Device operation The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
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M24C64-W M24C64-R M24C64-F  Device operation 4.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
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M24C64-W M24C64-R M24C64-F  4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). Table 2.
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M24C64-W M24C64-R M24C64-F  Instructions 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 4.
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M24C64-W M24C64-R M24C64-F  Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8. Figure 8.
PAGE 16
M24C64-W M24C64-R M24C64-F  Instructions 5.1.2 Page Write The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
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M24C64-W M24C64-R M24C64-F  5.1.3 Write Identification Page (M24C64-D only) The Identification Page (32 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction.
PAGE 18
M24C64-W M24C64-R M24C64-F  Instructions 5.1.6 Minimizing Write delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.
PAGE 19
M24C64-W M24C64-R M24C64-F  Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
PAGE 20
M24C64-W M24C64-R M24C64-F  Instructions 5.2.1 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.
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M24C64-W M24C64-R M24C64-F  5.4 Read the lock status (M24C64-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.
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M24C64-W M24C64-R M24C64-F  Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
PAGE 23
M24C64-W M24C64-R M24C64-F  8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range W) Symbol VCC TA fC Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C (1) 1 MHz Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C - 1(1) MHz Min. Max. Unit Supply voltage 1.7 5.
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M24C64-W M24C64-R M24C64-F  DC and AC parameters Table 9. AC measurement conditions Symbol Cbus Parameter Min. Load capacitance Max. Unit 100 SCL input rise/fall time, SDA input fall time - pF 50 ns Input levels 0.2 VCC to 0.8 VCC V Input and output timing reference levels 0.3 VCC to 0.7 VCC V Figure 12. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC MS19774V1 Table 10.
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M24C64-W M24C64-R M24C64-F  Table 11. Cycling performance by groups of four bytes Symbol Ncycle Parameter Write cycle endurance(2) Test condition(1) Max. TA  25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(3) 1. Cycling performance for products identified by process letter K. 2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
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M24C64-W M24C64-R M24C64-F  DC and AC parameters Table 13. DC characteristics (M24C64-W, device grade 6) Symbol Parameter Test conditions (in addition to those in Table 6) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC, device in Standby (SCL, SDA, E2, E1, mode E0) - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA 2.5 V < VCC < 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) - 2 mA 2.5 V < VCC < 5.
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M24C64-W M24C64-R M24C64-F  Table 14. DC characteristics (M24C64-R, device grade 6) Symbol Test conditions(1) (in addition to those in Table 7) Parameter Min. Max. Unit ILI Input leakage current ( SCL, SDA) VIN = VSS or VCC, device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 0.8 mA fc= 1 MHz(2) - 2.5 mA ICC Supply current (Read) ICC0 Supply current (Write) During tW,  1.
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M24C64-W M24C64-R M24C64-F  DC and AC parameters Table 15. DC characteristics (M24C64-F, M24C64-DF, device grade 6) Symbol Test conditions(1) (in addition to those in Table 8) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.7 V, fc= 400 kHz - 0.8 mA fc= 1 MHz(2) - 2.5 mA VCC = 1.7 V, fc= 400 kHz - 0.
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M24C64-W M24C64-R M24C64-F  Table 16. 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max.
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M24C64-W M24C64-R M24C64-F  DC and AC parameters Table 17. 1 MHz AC characteristics Parameter(1) Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tXH1XH2 tXL1XL2 Min. Max.
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M24C64-W M24C64-R M24C64-F  Figure 13. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (k ) 100 10 4k The R bus x Cbustime constant must be below the 400 ns time constant line represented on the left. R bu s × C bu s = Here Rbus × Cbus = 120 ns 40 VCC Rbus 0n s I²C bus master SCL M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Figure 14.
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M24C64-W M24C64-R M24C64-F  DC and AC parameters Figure 15.
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M24C64-W M24C64-R M24C64-F  9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 18.
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M24C64-W M24C64-R M24C64-F  Package mechanical data Figure 17. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45° A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A – – 1.750 – – 0.0689 A1 – 0.100 0.250 – 0.0039 0.0098 A2 – 1.250 – – 0.0492 – b – 0.280 0.
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M24C64-W M24C64-R M24C64-F  Figure 18. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B 1. Drawing is not to scale. Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. A – – 5.33 – – 0.2098 A1 – 0.38 – – 0.0150 – A2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.
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M24C64-W M24C64-R M24C64-F  Package mechanical data Figure 19. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead) D e MC b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 21.
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M24C64-W M24C64-R M24C64-F  Figure 20. WLCSP 5-bump wafer-length chip-scale package outline (M24C64-FCS6TP/K) e1 D 1 2 3 C e2 Detail A E e B A Index G A2 Index F A Side view Wafer back side Bump side Bump Detail A rotated by 90° A1 b 1Cd_ME 1. Drawing is not to scale. 2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). Table 22.
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M24C64-W M24C64-R M24C64-F  Package mechanical data Figure 21. Thin WLCSP 8-bump wafer-length chip-scale package outline (M24C64-DFCT6TP/K) e2 H D X Y e1 F Detail A E e e2 aaa Reference F A A2 (4X) Orientation G reference Bumps side Side view Wafer back side Bump A1 eee Z Z b Seating plane Detail A Rotated 90 ° 1Ci_ME_V2 1. Drawing is not to scale. 2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). Table 23.
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M24C64-W M24C64-R M24C64-F  10 Part numbering Table 24. Ordering information scheme Example: M24C64 - D W MN 6 T P /P Device type M24 = I2C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8) Device family Blank = Without Identification page D = With additional Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
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M24C64-W M24C64-R M24C64-F  Revision history 11 Revision history Table 25. Document revision history Date Changes 14-Mar-2011 22 Updated information concerning E2, E1, E0 for the WLCSP package: – note under Figure 3: 5-bump WLCSP connections (top view) – comment under Figure 5: Device select code – note 3 under Table 2: Device select code 07-Apr-2011 23 Updated MLP8 package data and Section Figure 56.: WLCSP 5 bumps package outline. Added footnote (a) in Section 4.5: Memory addressing.
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M24C64-W M24C64-R M24C64-F  Table 25. Document revision history (continued) Date Revision Changes Datasheet split into: – M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) for standard products (range 6), 28-Aug-2012 18-Nov-2013 27 28 – M24C64-125 datasheet for automotive products (range 3). Added 8-bump thin WLCSP. Updated single supply voltage and number of Write cycles on cover page. Updated Section 2.1: Serial Clock (SCL) and Section 2.2: Serial Data (SDA).
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M24C64-W M24C64-R M24C64-F   Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.